High performance low temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) with large grains were created using diode pumped solid state (DPSS) continuous wave (CW) laser lateral crystallization (CLC), employing fabrication processes at 450°C. Field-effect mobilities of 566 cm2/Vs for the n-channel and 200 cm2/Vs for the p-channel were obtained for a thick Si film (100–150 nm) on a 300×300 mm non-alkaline glass substrate. The high performance of the TFTs is attributed to the predominantly (100)-oriented very large grains. With a decreasing Si-film thickness, the grain size decreases, and the surface orientation of the grain changes from (100) to other orientations. These effects lead to reduced field-effect mobility with decreasing Si-film thickness, but it is easy to obtain a high field-effect mobility of over 300 cm2/Vs, even with a 50 nm thick Si film, without special processing techniques. A complementary metal oxide semiconductor (CMOS) ring oscillator was fabricated using a thin Si film 65 nm thick to demonstrate the high circuit performance of CLC poly-Si TFTs by applying the simplest CMOS process technology. A delay of 400 ps/stage at a gate length of 1.5 µm and a supply voltage of V dd=5.0 (V) was produced on a large non-alkaline glass substrate utilizing a fabrication temperature of 450°C. This crystallization method will lead to the fabrication of high-performance and cheap Si-LSI circuits on large non-alkaline glass substrates.

We studied the cluster size distribution of dislocation-free InAs͞GaAs self-assembled quantum dots obtained by the Stranski-Krastanow mode of molecular beam epitaxy. The same scaling function was obtained over a wide range of dot density. The scaling function indicated that the cluster size fluctuation, normalized by the average size, is constant for all the quantum dot densities studied. The resemblance of the scaling function to that of the submonolayer homoepitaxial growth implies that the strain is not the essential factor determining the cluster size distribution of quantum dots.[S0031-9007(98)05602-6] PACS numbers: 68.55. 61.43.Hv, 82.20.Mj The growth of lattice-mismatch semiconductor systems such as Ge͞Si and InAs͞GaAs has been known to produce a dotlike structure by the Stranski-Krastanow (SK) mode. Recently this growth mode, especially of InAs͞GaAs dots (known as "self-assembled quantum dots" [1]) has drawn much attention as a method to obtain quantum dots which are damage-free and fabrication-free. Now practical applications of quantum dots are seriously sought for, and efforts are being made in fabricating quantum dot lasers with predicted high performance such as a high characteristic temperature and a low threshold current. However, the current InAs quantum dots have a problem in size uniformity which is commonly about 610%, and is insufficient for laser applications. It is intriguing to know if this common size fluctuation is essential or accidental.Not to mention practical applications, the scaling property of two-dimensional (2D) island size distribution is known for submonolayer coverage. According to the scaling assumption [2,3], the island distribution is given byHere N s is the number of islands (normalized by the number of lattice sites) which contain s atoms, u is the fractional surface coverage, ͗s͘ is the average number of atoms in an island, and f͑x͒ is the scaling function, which depends only on s͗͞s͘. This scaling assumption was confirmed experimentally in Fe homoepitaxy [4] and InAs͞ GaAs heteroepitaxy [5].It is interesting to know if something similar to Eq. (1) holds for three-dimensional (3D) island growth by the SK mode, especially because it was reported [6] that the total island density r shows a power law as a function of the coverage expressed as r r 0 ͑u 2 u c ͒ a (2) for u from 1.5 to 1.9 monolayer (ML), where r 0 is the proportionality coefficient, u c is the critical coverage (1.5 ML), and the critical exponent a is 1.76. Equation (2) implies the presence of the scaling region and consequently the scaling function.In this Letter, we present the 3D island size scaling which holds for a quite wide range of the total density of the dislocation-free InAs͞GaAs islands by the SK mode.The growth was done by the Riber 2300 molecular beam epitaxy (MBE) system on a nominally flat GaAs (001) substrate. After the growth of the GaAs buffer layer at a substrate temperature of 600 ± C, growth was interrupted for 3-5 min, to decrease the temperature to 490 ± C to obtain a c͑4 3 4͒ surf...

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700–1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.

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