With a combination of outstanding properties and a wide spectrum of applications, graphene has emerged as a significant nanomaterial. However, to realize its full potential for practical applications, a number of obstacles have to be overcome, such as low-temperature, transfer-free growth on desired substrates. In most of the reports, direct graphene growth is confined to either a small area or high sheet resistance. Here, an attempt has been made to grow large-area graphene directly on insulating substrates, such as quartz and glass, using magnetron-generated microwave plasma chemical vapor deposition at a substrate temperature of 300 °C with a sheet resistance of 1.3k Ω/□ and transmittance of 80%. Graphene is characterized using Raman microscopy, atomic force microscopy, scanning electron microscopy, optical imaging, UV–vis spectroscopy, and X-ray photoelectron spectroscopy. Four-probe resistivity and Hall effect measurements were performed to investigate electronic properties. Key to this report is the use of 0.3 sccm CO 2 during growth to put a control over vertical graphene growth, generally forming carbon walls, and 15–20 min of O 3 treatment on as-synthesized graphene to improve sheet carrier mobility and transmittance. This report can be helpful in growing large-area graphene directly on insulating transparent substrates at low temperatures with advanced electronic properties for applications in transparent conducting electrodes and optoelectronics.

SiC-powered devices which reduce the power loss, size, and weight of power converters are gradually appearing in the power electronics market. From now on, cost reduction and quality improvement of SiC epitaxial wafers is required to further increase their popularity. This paper describes the state of development of mass production of the epi-wafer at Showa Denko K. K.

We investigated the carrot-defect reduction effect by optimizing the buffer layers of 4H-Silion Carbide (SiC) epitaxial wafers. The SiC epitaxial wafer with the 0.5 μm-thick optimized condition-B buffer layer show the carrot-defect density of 0.13 cm-2, since that with the conventional-A buffer layer were 0.68 cm-2. Although the average bunching length with the optimized condition-B buffer layer was 7-times longer than those with the conventional condition-A buffer layer, we could reduce the bunching length by applying the optimized condition-B only to the initial 0.05 μm-thick buffer layer. Finally, with the initial 0.05 μm-thick optimized condition-B buffer layers, we could achieve the SiC epitaxial wafers with only half the carrot-defect densities of those with the conventional condition-A buffer layers, while the average bunching lengths were less than 100 μm. With this condition, we could achieve the estimated yield of 90.1% with 4 x 4 mm chips, while that with the conventional condition-A buffer layer was 81.9%.

This study aims to fabricate copper oxide (CuO) nanowires by annealing a copper film formed on a charged film of fluorine-doped tin oxide (FTO). However, from the viewpoint of stress and growth of nanowires, it is difficult to mass-produce CuO nanowires on the entire region of the macro area on the plane substrate. In the proposed study, this was made possible by modifying the substrate’s structure.

As regards the copper oxide nanowire growth process, our experiment was consistent with the proposal of copper ions surface diffusion on a nanowire. Simply in the atmospheric pressure it is possible to synthesize CuO nanowires by annealing a copper sheet. Under a general copper oxide nanowires occurring condition, pouring the flow rate of a slight amount of air into an enclosed electric furnace in the atmospheric pressure, copper oxide nanowires adhering copper particles were synthesized on copper sheet successfully. In the growth process of the CuO wire, when the Cu substrate was heated in the air, stresses caused grain boundaries of Cu2O and CuO layers in the Cu substrate. Ultimately Cu ions formed a wire tip diffusing on the surface of a CuO wire in the vertical direction to the top surface of the CuO layer, while assembling to the tip. In this report, we describe characteristics of the structure of the CuO nanowire obtained by lowering the air flow rate.