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SiC -mixed Sn–58Bi composite solder bumps were successfully fabricated via an electroplating process. For the composite solder bump fabrication, ultrasonically dispersed SiC nanoparticles were added to the plating solutions. DSC analysis indicated that the melting temperature of SiC -mixed Sn–58Bi solders was the same as that of the non-mixed Sn–58Bi . Shear strengths of Sn–58Bi+SiC solder bumps were 6% higher than that of non-mixed solder bumps. The thicknesses of intermetallic compound were almost the same for both Sn–58Bi and Sn–58Bi+SiC samples. The Sn–58Bi+SiC composite solder bumps had finer lamellar structures than non-mixed Sn–58Bi . From the fracture surface analysis, fracture occurred at solder bump matrix, not at joint interface. Therefore, the addition of the SiC nanoparticles in the Sn–58Bi solders decreased the grain sizes, which increased the shear strengths.

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Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a 50µm of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

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