A large GaN-Schottky barrier diode (SBD) with a recessed dual anode metal is proposed to achieve improved the forward characteristics without a degradation of the reverse performances. Using optimized dry etch condition for a large device, the electrical characteristics of the device are demonstrated when applying the recessed dual anode metal and changing the recess depths. The device size and channel width are 4 mm 2 and 63 mm, respectively. The 16-nm recessed dual anode metal SBD has a turn-ON voltage of 0.34 V, a breakdown voltage of 802 V, and a reverse leakage current of 1.82 µA/mm at −15 V. The packaged SBD exhibits a forward current of 6.2 A at 2 V and a reverse recovery charge of 11.54 nC. Index Terms-AlGaN/GaN on Si, Schottky barrier diode (SBD), recess dual anode metal, low turn-on voltage. I. INTRODUCTIONG ALLIUM nitride (GaN) power devices are drawing greater attention in high-power switching applications owing to their superior power density, efficiency, and switching speed [1]. To achieve high efficiency and a small size in a power-conversion system, a low turn-on voltage (V T ), low on-resistance (R on ) and low reverse recovery of the diode are very important [2]. Various technologies to improve the performance of an SBD have recently been studied. Researches to reduce on-resistance and to reduce surface leakage current, such as SiO 2 , SiN x , Al 2 O 3 dielectric film, have been investigated [3]. In addition, studies on recess etching in the anode region and recess depth control have been actively conducted owing to the capability of recessed SBDs to reduce the V T without an increase in the leakage current [4]-[6]. However, for large device fabrication, the dry etch conditions including a uniform etch profile, a reproducible etch rate, and a small amount of plasma damage are very difficult and Manuscript

A low onset voltage AlGaN/GaN diode with a width of 14 mm is achieved. The recess depth of the AlGaN layer is responsible for the low onset voltage. In comparison with the conventional non-recessed diode, the onset voltage reduces by 45% along with a decrease of reverse leakage current by about one order of magnitude.

In this paper, we present the design and characterization analysis of a cascode GaN field‐effect transistor (FET) for switching power conversion systems. To enable normally‐off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement‐mode Si metal‐oxide‐semiconductor FET and a high‐BV depletion‐mode (D‐mode) GaN FET. This paper demonstrates a normally‐on D‐mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO‐254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of 250 μA, and an on‐resistance of 331 mΩ. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

In this article, we demonstrate a 9.7–12.9‐GHz monolithic microwave integrated circuit low‐noise amplifier (LNA) designed and fabricated using a AlGaN/GaN 0.25‐µm high‐electron mobility transistor on silicon carbide (SiC) technology. Microstriplines are used for matching circuits, except for the MIM capacitors acting as DC blocks in the matching circuits of the LNA circuit. The matching and bias circuits of the LNA are merged and meandered to simplify the structure of the amplifier and reduce the chip size. The LNA shows a noise figure of 1.7–2.1 dB with a small‐signal gain of 20–26 dB and an isolation of 45–52 dB across the 9.7–12.9 GHz frequency range. Under continuous wave conditions, a saturated output power of 34 dBm is shown at 11.2 GHz, and an output third‐order intercept point of 42 dBm is also achieved at 11.4 GHz. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:96–99, 2014