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In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE) array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.This new approach provides for a high performance, cost effective, gain over software simulation. Simulation results show that the hardware accelerator is orders of magnitude faster than the software simulation program.

This paper provides eflcient design verification methodologies based on concurrent simulation technique which is implemented zn the interactive simulation automation system (ISAS). Concurrent simulation is not a new technique, however, the ISAS exploits many parallelisms during the simulation procedure and applies it to three different types of simulation: concurrent (C-sim), distributed concurrent (De-sim), and concurrent-concurrent (CON2FERS). ISAS automates the simulation procedure with a graphic user interface and handles not only fault models, but also desagn error models. It generates fault and design error coverage metrics for the user. This paper provides a description of three types of concurrent simulators with performance results.