In this study, power/ground noise suppression structures were designed based on a proposed dispersion analysis for packages and interposers with low-loss substrates. Low-loss substrates are suitable for maintaining signal integrity (SI) of high-speed channels operating at high data rates. However, when the power/ground noise is generated in the power delivery network (PDN), low-loss substrates cannot suppress the power/ground noise, thereby causing PDN-induced crosstalk and various power integrity (PI) issues. To solve these issues, noise suppression structures generating electromagnetic bandgap were proposed and designed. The mechanism of the proposed structures was examined based on a proposed dispersion analysis. The proposed structures were designed and fabricated in glass interposer test vehicles, and the effectiveness of the structures on power/ground noise suppression was experimentally validated by measuring the noise suppression band. The proposed dispersion analysis was also verified by comparing the derived noise stopband edges (fL and fU) with electromagnetic (EM) simulation and experimental results, and they all showed good agreement. Compared to EM simulation, the proposed method required smaller computational resources but showed good accuracy. Using the proposed dispersion analysis, various power/ground noise suppression bands were designed considering the applications and design rules of packages and interposers. With measurements and EM/circuit simulations, the effectiveness of the designed structure in maintaining SI/PI was verified. By adopting the designed structures, the noise transfer properties in the PDN were suppressed in the target suppression frequency band, which is key for PI design. Finally, it was verified that the proposed structures were capable of suppressing power/ground noise propagation in the PDN by analyzing PDN-induced crosstalk in the high-speed channel.

Electromagnetic (EM) remote visualization of screen images attacks (RVSIAs) is among the most actively researched topics in hardware security. Target displays are being developed daily; for example, recently developed high-resolution displays have multiple divided areas on the screen, and each area transmits different pixel information. In this case, it is difficult to reconstruct the screen using the conventional methods because the target screen information is leaked by multiple lines at the same frequency and timing, and multiple screen information is mixed into the EM waves. By contrast, in this article, we propose a novel RVSIA method that focuses on the difference in the transfer functions of multiple emanations from a high-resolution display. Considering the structure and signal transmission method of recent high-resolution displays, the proposed attack method observes leaked EM waves from multiple observation positions and alters the receiving frequencies of the receiver. For the first time, we have been able to separate multiple screen information contained in leaked EM waves using an independent component analysis method. In the experiments, we applied the proposed method to an actual laptop PC that divides the screen into multiple areas. As a result, it was possible to reconstruct screen information using the proposed attack method. Thus, the proposed method enables successful attacks against recent high-resolution displays. Furthermore, the measurement equipment employed remains similar to those utilized in the conventional attacks.

In encryption circuits, the threat of fault injection analysis remains a considerable problem. More specifically, clock glitches generated by intentional electromagnetic (EM) irradiation cause faulty operations and estimate internal secret keys. Generating clock glitches via intentional EM interference (IEMI) can be performed without opening the equipment, which makes it a real threat. Previous secret key analysis via IEMI has focused on setup time violations. It requires the clock glitch to occur near the critical path delay of the encryption circuit. This article examines the faults owing to timing violations of inputs to the sequential circuit and discusses the possibility of obtaining the secret key from the output of the faulty ciphertext. The input timing violation of the sequential circuit covers all times during the operation. The bias of the output value of the sequential circuit owing to input timing violations is evaluated using a measurement system in which the sequential circuit alone was extracted. Secret key analysis of encryption circuits using the bias of output values is performed for three different implementations of the advanced encryption standard to demonstrate its feasibility. The results indicate that secret key analysis is possible over a wide range of shortened clock period, regardless of the implementation method.

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