3D-Network-on-Chips exploit the benefits of Network-on-Chips and 3D-Integrated Circuits allowing them to be considered as one of the most advanced and auspicious communication methodologies. On the other hand, the reliability of 3D-NoCs, due to the vulnerability of Through Silicon Vias, remains a major problem. Most of the existing techniques rely on correcting the TSV defects by using redundancies or employing routing algorithms. Nevertheless, they are not suitable for TSV-cluster defects as they can either lead to costly area and power consumption overheads, or they may result in non-minimal routing paths; thus, posing serious threats to the system reliability and overall performance. In this work, we present a scalable and low-overhead TSV usage and design method for 3D-NoC systems where the TSVs of a router can be utilized by its neighbors to deal with the cluster open defects. An adaptive online algorithm is also introduced to assist the proposed system to immediately work around the newly detected defects without using redundancies. The experimental results show the proposal ensure less than 2% of the routers being disabled, even with 50% of the TSV clusters defects. The performance evaluations also demonstrate unchanged performances for real applications under 5% of cluster defects.

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Spiking neural networks (SNNs) are artificial neural network models that more closely mimic biological neural networks. In addition to neuronal and synaptic state, SNNs incorporate the variant time scale into their computational model. Since each neuron in these networks is connected to thousands of others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, very low communication latency is also needed. The 2D-NoC was used as a solution to provide a scalable interconnection fabric in large-scale parallel SNN systems. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. The combination of these two emerging technologies provides a new horizon for IC designs to satisfy the high requirements of low power and small footprint in emerging AI applications. In this work, we first present a comprehensive analytical model to analyze the performance of 3D mesh NoC over variants of different SNN topologies and communications protocols. Second, we present an architecture and a low-latency spike routing algorithm, named shortest path K-means based multicast (SP-KMCR), for three-dimensional NoC of spiking neurons (3DNoC-SNN). The proposed system was validated based on an RTL-level implementation, while area/power analysis was performed using 45nm CMOS technology.

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication.In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC) 1 . In addition, we present detailed complexity and performance evaluation of the proposed architecture.