This work presents our improvement of the failure localization techniques of logic circuits using voltage contrast (VC) in yield enhancement. VC analysis is known as a useful technique for finding defects by comparing scanning electron microscope (SEM) images of a faulty device with those of a good device. However, the observation region in VC analysis should be narrowed down in advance and then failure analysis (FA) engineers need to find small differences in the SEM images in order to make it effective. We improved the software tools of the scan-based diagnosis and VC analysis support to overcome these difficulties. A hybrid technique using the fail data in both the bypass and compression modes in chain fault diagnosis reduces the diagnosis time while suppressing the amount of data explosion concerning the faulty chains. In VC analysis, accurate VC images were emulated from the design layout by taking into account the states of the transistors in the FA phase such as the "on/off" states, gate leakage, and short to ground of the power lines. FA engineers can localize the fault sites with an anomalous contrast by cross-matching between a SEM image of a faulty device and the emulated VC image without using a SEM image of a good device. These techniques accelerate the failure localization in yield enhancement and we demonstrate some examples in this paper.

We propose a phase image simulation method for Electro-Optical Frequency Mapping (EOFM). The proposed method eases the matching of phase images and circuit layout data, which was previously difficult because phase images are very complex. Physical failure analysis based on this matching result is enabled. Further works are required for understandings of simulated phase images in compound logic cells having many states or high-Z states.