No abstract

In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESDtransient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESDtransient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.978-1-4244-9474-3/11/$26.00 ©2011 IEEE

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.978-1-4244-5271-2/10/$26.00 ©2010 IEEE

a) (b) Fig. 1. A NOT gate simulation results (a) propagation delay time and (b) output transition time with different input transition time and output capacitance loadings. Abstract I. INTRODUCTIONto design power efficient ICs. One way is to utilize flexible power supply. In the power flexible system, the circuit may be operated in ultra-low voltage. Due to the circuits work in ultra-low voltage domain, the power consumption can be reduced greatly. Based on this feature, it is appealing to implement a circuit system in ultra-low supply voltage. For digital signal processing systems, multipliers are essential blocks which used to accomplish the arithmetic operation. Thus, it is meaningful to create a multiplier which is suitable for ultra-low voltage operation. However, circuits designed in ultra-low voltage domain encounter shrinking gate-source voltage of MOS devices, which lower current driving capability of MOS devices, and the operation speed is limited. Therefore, the design of a high-speed multiplier with ultra-low supply voltage is a challenging task. The most straight forward way to improve the performance of MOS devices in ultra-low voltage domain is using low-V T devices. However, additional masking steps raise the cost of a chip. To avoid this, we utilize forward body bias technique [1] to speed up operation rate by lowering the threshold voltage of MOS devices. While using the forward body bias technique may increase the leakage current from the forward diode of MOS devices, but the leakage power in the ultra-low voltage circuit is smaller than the one in the higher voltage circuit. Furthermore, since PMOS can be independently fabricated in N-well without additional masking steps, it is easy to apply the forward body bias technique in PMOS device than in NMOS.Although the PMOS forward body bias technique is applied, the circuit driving capability is still not enough to make the system operate at high speed rate. Fig. 1(a) demonstrates the propagation delay time of a NOT gate, which is strongly related to the input transition time and the output capacitance loadings in 0.5-V PMOS FBB (Forward Body Bias) than those in 1.

A rail-to-rail constant gain CMOS operational amplifier was designed by using complementary differential input stage and current compensation skills. The chip was implemented by a 0 . 3 5~1 1P4M CMOS standard logic process. The measurement results show that the chip can achieve 1lOdB gain, 13.6MHz bandwidth, and 1.275mW power consumption, when operating at 3V and 35pF load.