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The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

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Among the most fundamental challenges encountered in the successful incorporation of graphene in silicon-based electronics is the conformal growth of ultrathin dielectric films, especially those with thicknesses lower than 5 nm, on chemically inert graphene surfaces. Here, we present physisorbedprecursor-assisted atomic layer deposition (pALD) as an extremely robust method for fabricating such films. Using atomic-scale characterisation, it is confirmed that conformal and intact ultrathin Al 2 O 3 films can be synthesised on graphene by pALD. The mechanism underlying the pALD process is identified through first-principles calculations based on density functional theory. Further, this novel deposition technique is used to fabricate two types of wafer-scale devices. It is found that the incorporation of a 5 nm-thick pALD Al 2 O 3 gate dielectric film improves the performance of metaloxide-graphene field-effect transistors to a greater extent than does the incorporation of a conventional ALD Al 2 O 3 film. We also employ a 5 nm-thick pALD HfO 2 film as a highly scalable dielectric layer with a capacitance equivalent oxide thickness of 1 nm in graphene-based tunnelling field-effect transistors fabricated on a glass wafer and achieve a subthreshold swing of 30 mV/dec. This significant improvement in switching allows for the low-voltage operation of an inverter within 0.5 V of both the drain and the gate voltages, thus paving the way for low-power electronics.

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