Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

Abstract

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

Single-Atom Catalysts for Electrochemical Hydrogen Evolution Reaction: Recent Advances and Future Perspectives

“…Although using the ALD method, some noble metal Ru, Pt, and Pd SACs can be successfully grown on several types of substrates, such as SiO 2 , Al 2 O 3 , and TiO 2 [52,[137][138][139][140]. It still suffers from low yields, high cost of equipment, and precursors, which is not favorable for widespread production [141][142][143].…”

Insulators for 2D nanoelectronics: the gap to bridge

“…3c we compare the experimental values for the gate leakage currents in test structures and complete devices from Si [59][60][61][62] and 2D 39,46,[63][64][65][66] technologies. In agreement with theoretical predictions, the lowest gate leakage currents have been obtained for HfO 2 65 , which has the highest permittivity of 25, and for CaF 2 46,62 , which is a crystalline and thus mostly defect-free insulator with a bandgap of 12.1 eV. Also, we note that epitaxial oxides like La 2 O 3 or Gd 2 O 3 have been previously considered for applications in Si devices 61,67 , and they may be a promising option for scaled 2D FETs as well.…”

“…For defective oxides, trap-assisted tunneling can lead to a significant contribution at low voltages, which is not accounted for in our best-case model. c Experimental gate leakage currents versus EOT measured at standard FET operating gate voltages 1-3 V. Literature data shown with open symbols for Si-based [59][60][61][62] and filled symbols for 2D-based structures 39,40,46,[63][64][65][66] .…”

Improving Performance of Tin-Doped-Zinc-Oxide Thin-Film Transistors by Optimizing Channel Structure

“…7,8 TFTs based on 2-dimentional (2D) materials such as graphene and Molybdenum disulfide (MoS2) have been widely investigated recently due to their excellent electrical properties. 9,10 However, 2D materials-based TFTs still have some challenges in large-scale fabrication of high quality devices, not compatible with modern Silicon-based microelectronic technologies. Zinc-oxide (ZnO) based TFTs have attracted considerable attention for their superior electrical and optical properties since last decade.…”