No abstract

No abstract

Glass (7740) and silicon (100) wafer are bonded using gold as the bonding medium and annealed to enhance the bonding strength at temperature about 450 . The voids in the bonding interface are the main reason to cause the poor reliability of bonding, and scanning electron microscope (SEM) photos reveal that there are a number of voids in the craters on the surface of silicon wafer after bonding. It is observed that the voids appear with the increase of sizes of the local bonded areas (reaction areas); that is to say, the bigger the local bonded areas are, the larger possibility to form the voids in the craters. Considering the analyses above, a new model is proposed to test the relationship between the voids and the local reaction areas, and the SEM pictures suggest that when the sizes of the reaction areas are larger than 5 m, the voids will form in the craters obviously. In other words, the eutectic alloys are insufficient to replenish the cavities generated by the diffusion of silicon when the sizes of the reaction areas are beyond 5 m.

We present a generic three-dimensional (3-D) integration method to fabricate suspended single crystalline silicon (SCS) MEMS arrays on CMOS. The method is based on transferring the SCS device layer of SOI on the top of CMOS. For general purpose, thin MEMS arrays with long supporting arms are demonstrated. The fabrication process is clarified in details. Mechanical reliability of the suspended structure is addressed with drop tests and is improved by optimizing the Cu plating parameters. The residue stress is compensated by tailoring the thickness of the oxide layer and flat free-standing structures are achieved. This method is applicable to a large variety of SCS MEMS including accelerometers, gyroscopes, micro-mirrors, RF MEMS switches, and resonators.