Bandwidth interleaving digital-to-analog converter (BI-DAC) is a new method for breaking through the bandwidth restriction of the DAC to generate a wideband signal. However, there are some errors in the BI-DAC system such as the aliasing errors caused by the non-ideal performance of the analog filters. To achieve the aliasing errors cancellation, this paper studied the minimax design of digital finite impulse response (FIR) filters. The design goal was to meet a given desired spurious free dynamic range (SFDR) of the BI-DAC system. The problem of designing the digital FIR filters was formulated as a linear programming (LP) problem which could be used to find the global optimal solution of the coefficients of the digital FIR filters. Additionally, this proposed design method performance analysis consist of the computational complexity was derived. Finally, all the proposed designs are verified by both theoretical analysis and numerical simulations, and satisfactory simulation results were achieved.

Pattern jitter is a primary contributor to the increase of the bit error rate (BER) in high-speed communications, which occurs in large part due to duty cycle distortion (DCD). By considering DCD caused by transmission links and the distribution of jitter in DCD due to the pattern of the transmission link, this paper proposes a precise control method based on the cross point of the eye diagram to minimize the jitter associated with DCD and to effectively decrease the BER of high-speed digital communications. By capitalizing on the theoretical basis that the main form of DCD is the offset of the cross point of the eye diagram, the technology presented here reconstructs the pattern waveform by using a digital method and incorporates a time variable to precisely control the data edge position during the reconstruction process, thereby stabilizing the cross point at 50% to correct its drift. Accordingly, after fanning out the original pattern buffer and then passing two controllable delay lines with different delays through the buffer in a process that is driven by digital logic operation, the cross point of the waveform is reconstructed by changing the relative time delay of the two signals. As a result, the change in the position of the cross point of the eye diagram is transformed into the precise control of the relative time delay, minimizing the DCD jitter. The theoretical model is verified by experiments, indicating that this method can control the cross point of the non-return-to-zero (NRZ) pattern in the range of 30% to 70% under 3 Gbps with a resolution as great as 1%. Furthermore, this approach can solve the problem of cross point drift of the eye diagram and can significantly decrease the BER caused by DCD jitter.INDEX TERMS Cross point of the eye diagram, pattern jitter, duty cycle distortion (DCD), bit error rate (BER).

Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.

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