Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.

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Copper as a metal of choice for interconnection purposes, needs damascene approach to realize the interconnect formation. This approach needs etch stop layers to form via and trench. Metal and dielectric barriers are also needed to prevent Copper from diffusing into the substrate. The integrity and adhesion of all these different layers is a subject of great concern from the yield standpoint. The problem needs more careful attention with porous low k dielectric material. In this paper, some aspects related to the adhesion of the various thin films that form the damascene stack are discussed. Analysis of failures/outliers encountered during routine die pull test is also done. The failure analysis performed on such failures provided a very good insight into the weakness in the dielectric stack, that form the interconnect, in the case of device with Copper as back-end metallisation. Techniques to improve the adhesion of various layers and other novel approaches used to improve the process margin are also discussed. Relationship between the die size and stress induced dielectric delamination is also discussed in this paper.