Fault tolerant is one of major requirements for embedded systems. As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of faults.Faults is the sources for low dependability, faults can be hardware and software. Hardware faults can be distinguished from systematic faults like software or design errors. The Fault can be deleted, such as extensive testing or formal verification and tolerated by fault tolerance techniques. We restrict ourselves to the problem of fault tolerance and refer to other methods for troubleshooting.This paper discusses a new design method about the fault tolerant system of embedded system. We designed a fault tolerant system of data acquisition system in dynamically re-configurable FPGA. The experiment results show that the system not only be able to higher self-adaptive ability and reliability, but also can Through the FGPA to complete a specific algorithm.

More and more applications need The ability to customize the architecture to match the computation and the data flow of the application, so increasingly new system implementations based on reconfigurable computing are being considered. Reconfigurable computing has potential to accelerate a wide variety of applications; its main feature is the ability to perform computations in hardware to improve performance, while retaining the flexibility of software solutions. An operating system (OS) for reconfigurable computing uses new versions of algorithms for the scheduling, the operating system must decide how to allocate the hardware at run-time based on the status of the system. This paper discusses the scheduling algorithm for reconfigurable computing platform, covers two aspects of reconfigurable computing: architectures and design methods. The tasks are divided into two categories in this survey, consider the issues involved in reusing the configurable hardware during program execution. And improve μC/OS-II to manage the use of reconfigurable resources, responsible for task scheduling, helping the programmer to concentrate more on application development.

Data acquisition begins with the physical phenomenon or physical property to be measured. Examples of this include temperature, gas pressure, and light intensity, and force, fluid flow, regardless of the type of physical property to be measured. Physical property converted into digital, and then by the computer for storage, processing, display or printing process, the corresponding system is called data acquisition system. With the rapid development of computer technology, data acquisition systems quickly gained popularity. A variety of products based on digital technology have been created. Digital System spread quickly; it’s mainly the following two advantages: the first is the digital processing flexible and convenient; the second is a digital system is very reliable. The main idea of Reconfigurable computing technology [1] is using the FPGA [2][3] allows the system has a dynamically configurable capacity, suitable for harsh environment applications, improve the speed of data processing. By the use of dynamic reconfigurable FPGA devices can be realized on the hardware logic function modification, application of reconfigurable computing technology can improve the speed of data processing. Data acquisition system is widely applied in many fields, and often used the abominable working environment place. The reconfigurable computing technology, can greatly improve the data acquisition system reliability and safety. The paper introduces a kind of multi-channel data acquisition system based on USB bus and FPGA, the factors affecting the performance of system are discussed, and describes how to use reconfigurable computing technology to improve the efficiency of data acquisition system while reduce energy consumption. The system in this paper uses AD's AD9220, ALTERA's EP1C6-8 and IDT's IDT70V24, Cypress’s CY7C68013.