A low-cost fault-tolerant finite impulse response (FIR) filter is presented to save logic resources. Based on the redundant residue number system (RRNS), it eliminates soft errors generated by single event upset (SEU) in space applications, which requires only one three-moduli set residue to binary converter based on the Chinese remainder theorem. When a soft error happens, only one small-sized first-in-first-out and rollback operations are needed to refresh the FIR filter corrupted by SEU. Theoretical analysis and fault injections are performed to validate that there is no fault missing event. In addition, the proposed scheme can save 21% cell area compared with the conventional RRNS method.Introduction: Single event upset (SEU) is one of the most serious effects in space applications, which alters the state of a flip-flop or memory cell resulting in a soft error. It could reduce the reliability of space communications and produce bit errors if no action is taken [1].Finite impulse response (FIR) filters with a multiply and accumulation structure are popular in digital communications. Furthermore, the fault-tolerant FIR filter has been widely investigated for space communications. Triple modular redundancy (TMR) [2] is the commonly used mitigation technique but consumes more than three times hardware resource compared with its non-fault-tolerant counterpart. The redundant residue number system (RRNS) [3] is a simplified fault-tolerant method, whereby the normal FIR filter is transformed to several modular ones with reduced word length. However, it usually requires one or more four-moduli set residue to binary converters (RTBCs) based on the Chinese remainder theorem (CRT) to detect or correct a soft error. For a delicately designed four-moduli set RTBC, the hardware complexity is about O(n 2 + 12n + 12) [4], whereas the three-moduli set RTBC is O(9n + 1) [5], n is defined as the uniform word length of each modulus. Hence, it leads to a large area reduction for the conventional RRNS to replace the four-moduli set RTBC by the three-moduli set counterpart. Although the architectures proposed in [6,7] require no RTBC, two identical FIR filters plus a checking module based on residue code are required. Besides requiring more than twice the hardware resources, the former exists fault missing event and the latter introduces additional noise at the FIR outputs. To solve these problems, a low-cost fault-tolerant FIR filter based on RRNS is developed, which requires only one three-moduli set RTBC and could correct all single errors leading to a zero fault missing event.

An ASIC implementation scheme of a fractionally spaced Rake (FS-Rake) receiver is presented for high data rate UWB systems to save hardware resources and avoid routing congestion. In this scheme, one pre-combining module and two stages of shift register and multiplexer are employed for multipath selection. ASIC implementation results demonstrate that the proposed scheme can save 13.1% cell area compared with the conventional FS-Rake structure. More importantly, routed nets are reduced by 37.2%. Therefore, serious routing congestion that is an obstacle to design convergence is mitigated effectively in this proposed scheme.Introduction: In ultra-wideband (UWB) systems, the Rake receiver that can provide diversity gain in multipath fading channels is always attractive for signal detection [1]. A fractionally spaced Rake (FS-Rake) can capture more energy and is much less sensitive to synchronisation errors, thus it achieves better performance than other Rake receivers [2, 3]. However, this high resolution FS-Rake costs higher hardware resources. In Rake implementation, shift registers and multiplexers are commonly utilised for multipath selection [4]. According to the UWB long spread delay channel conditions [5], the stage number of shift registers in a FS-Rake may be as large as several hundred to ensure that all the multipath components have fallen into the desired span. Moreover, in high data rate UWB systems, the stringent timing constraint and huge number of routed nets between shift registers and multiplexers can cause serious routing congestion and even result in design unconvergence. To solve these problems, a novel FS-Rake structure with one pre-combining module and a two-stage multipath selection part is proposed for ASIC implementation of high data rate UWB systems.

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