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For massive multiple-input multiple-output (MIMO) systems, linear minimum mean-square error (MMSE) detection has been shown to achieve near-optimal performance but suffers from excessively high complexity due to the large-scale matrix inversion. Being matrix inversion free, detection algorithms based on the Gauss-Seidel (GS) method have been proved more efficient than conventional Neumann series expansion (NSE) based ones. In this paper, an efficient GS-based soft-output data detector for massive MIMO and a corresponding VLSI architecture are proposed. To accelerate the convergence of the GS method, a new initial solution is proposed. Several optimizations on the VLSI architecture level are proposed to further reduce the processing latency and area. Our reference implementation results on a Xilinx Virtex-7 XC7VX690T FPGA for a 128 base-station antenna and 8 user massive MIMO system show that our GSbased data detector achieves a throughput of 732 Mb/s with closeto-MMSE error-rate performance. Our implementation results demonstrate that the proposed solution has advantages over existing designs in terms of complexity and efficiency, especially under challenging propagation conditions. Index Terms-Massive MIMO, minimum-mean square error (MMSE), Gauss-Seidel method, soft-output data detection, VLSI. I. INTRODUCTIONT HE transmission of multiple data streams concurrently and in the same frequency band, which is known as multiple-input multiple-output (MIMO) technology, enables higher data rates compared to traditional single-input singleoutput (SISO) wireless communication systems [2]. Due to the combined effect of the ever-growing mobile data traffic and the scarcity of favorable radio spectrum in the low-loss frequency range, massive MIMO is widely believed to be a core technology for upcoming fifth generation (5G) wireless communication systems [3]. Massive MIMO promises higher data rates, improved spectral efficiency, better link reliability, and coverage over small-scale MIMO systems [4][5][6][7][8][9]. Compared to SISO systems, multiple interfering messages/symbols are transmitted concurrently in MIMO systems and expected to be separated at the receiver side with the contamination of noise or interference [10]. In the case of massive MIMO, however, this data detection operation entails excessively high computational

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In massive MIMO (M-MIMO) systems, one of the key challenges in the implementation is the large-scale matrix inversion operation, as widely used in channel estimation, equalization, detection, and decoding procedures. Traditionally, to handle this complexity issue, several low-complexity matrix inversion approximation methods have been proposed, including the classic Cholesky decomposition and the Neumann series expansion (NSE). However, the conventional approaches failed to exploit neither the special structure of channel matrices nor the critical issues in the hardware implementation, which results in poorer throughput performance and longer processing delay. In this paper, by targeting at the correlated M-MIMO systems, we propose a modified NSE based on tridiagonal matrix inversion approximation (TMA) to accommodate the complexity as well as the performance issue in the conventional hardware implementation, and analyze the corresponding approximation errors. Meanwhile, we investigate the VLSI implementation for the proposed detection algorithm based on a Xilinx Virtex-7 XC7VX690T FPGA platform. It is shown that for correlated massive MIMO systems, it can achieve near-MMSE performance and 630 Mb/s throughput. Compared with other benchmark systems, the proposed pipelined TMA detector can get high throughput-to-hardware ratio. Finally, we also propose a fast iteration structure for further research.Index Terms-Massive MIMO (M-MIMO), linear detection, matrix inversion approximation (MIA), VLSI design, FPGA.