A power-efficient and low-cost 1.0625-3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel (FC), Peripheral Component Interconnect Express (PCIe), and RapidIO applications. To support multiple standards with a single low power and low cost design, the transceiver presented here uses a wide swing range source-series-terminated (SST) transmitter (TX), a passive receiver (RX) equalizer, a dual-loop phase locked loop (PLL) and a mixed signal clock and data recovery (CDR) unit. The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver. The dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR's reference. A CDR with a phase interpolator (PI) is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 ppm. The transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 mm 2. With supply voltages of 1.2 V and 3.3 V, the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at 3.125 Gb/s.

In this paper, a 2.125GBd 10bit Serialize/Deserialize (SERDES) system has been implemented, transmitter section and receiver section are capable of working simultaneously. A new architecture of CDR and PLL has been proposed. The same coarse loop is used in the PLL and CDR to set each digital control bits of VCO. And a pre-emphasis driver is utilized to compensate for the high frequency attenuation in channel. The measurement results show that SERDES has a RMS jitter of 28ps.

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