An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor's series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.

Hardware implementation of LTE-Advanced systems using FPGA and ASIC technology is a highly promising technology. This article proposed a reliable and effective architecture for a LTE downlink transmitter under different antenna configurations including SISO 1×1; MIMO 2×2. The design has been synthesized using Altera Quartus II 13.1.4 on Altera Stratix-V 5SGSMD8K2F40I2. The parameter improving cost is introduced to evaluate the upgrading of resources caused by performance improvement. With this proposed structure, improving cost can be reduced compared with traditional method. The proposed plan is fabricated as an ASIC using SMIC 55-nm CMOS technology. Finally, the design is demonstrated in the test platform, showing a successful performance.