No abstract

To explore the possibility of soft IP implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or SOC on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the thermally sensitive pulse with a width proportional to the measured temperature. The timing reference is just the input clock, and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit is realized by FPGA chips for functionality verification and performance evaluation. Implemented with as few as 140 Logic Elements, the proposed smart sensor was measured to have an error of -0.7°C40.9°C over a wide temperature range of -40°C-130°C. The effective resolution is better than 0.1°C, and the power consumption is 8.42pW at a sample rate of 2 samples/s. The performance is as good as those of most full-custom predecessors. The longest conversion time is around 260ps, and a conversion rate of 3 kHz at least is promised.Index Terms-temperature sensor, smart sensor, fully digital smart sensor, cyclic delay line, time domain, on-chip integration, low cost.