this paper presents a high speed low voltage differential signal (LVDS) interface circuit for CPU, LCD, FPGA and other fast links. In the proposed transmitter a stabile reference and a common mode feedback circuit are applied into the LVDS drivers, which enable the transmitter to tolerate the variations of process, temperature and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture which allows a 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3v, 0.18 エ CMOS technology. Transmission operations up to 1.6Gb/s with random data patterns were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 35mW and 6mW respectively.

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