0.12 μm hole pattern formation by KrF lithography for Giga bit DRAM

Nakao, S.; Nakae, Aya; Yamaguchi, A.; Kimura, Hideo; Ohno, Yasuo; Matsui, Yasuji; Hirayama, M.

doi:10.1109/iedm.1996.553122

Cited by 8 publications

(7 citation statements)

References 2 publications

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“…All of the approaches in the literature for regularly placed contacts place contacts regularly in both directions at the same time. 14,15,20,22 Second, although the horizontal resolution ͑single exposure͒ can be improved by a regularly placed layout, the desired horizontal grid pitch ͑1/2 transistor pitch͒ is still smaller than the improved resolutions of both contact and gate layers. Multiple exposures must be introduced to fabricate the new layout.…”

Section: Lithographic Approachesmentioning

confidence: 99%

“…Many lithographic approaches have been proposed for the regularly placed layout. [13][14][15]17,18,20,22,23 There are mainly two kinds: assist feature approaches 15,20,22 and template-trim mask approaches. 13,14,17,23 Assist features are added around isolated features in assist feature approaches to improve the process latitude.…”

Section: Lithographic Approachesmentioning

confidence: 99%

“…Based on the OAI or an alternating phase-shifting mask ͑alt-PSM͒, many advanced lithographic approaches have been proposed recently for contacts and gates that employ regular layout placement, pushing the k 1 to about its minimum value. [11][12][13][14][15][16][17][18] However, on the other hand, from a layout designer point of view, the regular placement imposes extra restriction on layout compaction. Although the gates and contacts can be designed smaller and packed closer, the regular placement may be so restrictive on layout compaction that the final circuit area increases unacceptably.…”

Section: Introductionmentioning

confidence: 99%

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Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Wang

Wong²,

Lam

2005

J. Micro/Nanolith. MEMS MOEMS

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The practicability and methodology of applying resolutionenhancement-technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from Ϫ4.2 to Ϫ15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from Ϫ16.2 to ϩ2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Photo-Optical Instrumentation Engineers.

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Section: Lithographic Approachesmentioning

confidence: 99%

Section: Lithographic Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Wang

Wong²,

Lam

2005

J. Micro/Nanolith. MEMS MOEMS

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“…18 Figure 5͑a͒ is a top-down SEM view of such a hole grating etched into silicon nitride. 18 Figure 5͑a͒ is a top-down SEM view of such a hole grating etched into silicon nitride.…”

Section: Pillars and Holesmentioning

confidence: 99%

Nanofabrication with deep-ultraviolet lithography and resolution enhancements

Fritze

Palmateer

Maki

et al. 1999

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested in Improvement of imaging properties by optimizing the capping structure in extreme ultraviolet lithography Absorber stack with transparent conductive oxide layer for extreme ultraviolet lithography This work explores the nanofabrication potential of resolution-enhanced deep-ultraviolet lithography. We combine strong phase-shift methods with fabrication-based enhancements to produce silicon structures in the deep sub-100 nm regime. Limits on resolution and pitch with these methods are considered.

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“…Nakao et al defined a square lattice pattern by using a double-exposure method. 12) In this double-exposure method, a wafer is exposed to light through two line-and-space-(L/S)pattern masks in two perpendicular directions. Therefore, the resolution limit of the lattice pattern is almost the same as that for the L/S patterns.…”

Section: Introductionmentioning

confidence: 99%

Red-Emitting Organic Electroluminescent Devices with Tetraphenylchlorin Doped into a Hole-Transporting Material

Bera¹,

Sakakibara²,

Tokumoto³

et al. 2002

Jpn. J. Appl. Phys.

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We have developed a triple-exposure method for defining a triangular-lattice pattern to form two-dimensional (2D) photoniccrystal (PC) waveguides operating at a 1.55-µm wavelength. This method, in which three line-and-space (L/S) patterns are projected onto a wafer in three different directions, allows us to define a smaller-pitch triangular-lattice pattern compared to that definable by the conventional exposure method. When 0.61-µm-pitch L/S masks were employed, an i-line stepper successfully resolved a 0.7-µm-hole-pitch triangular-lattice pattern, which was at the resolution limit. A sharply bent line defect was introduced as a waveguide into the pattern by using L/S photomasks with the corresponding parts of the space areas removed. We applied this method to fabricate a triangular-lattice 2D PC with a hole pitch of 0.8 µm and a minimum feature size of 0.05 µm. The measured photonic bandgap (PBG) of this PC indicated that it operates at a near-1.55-µm wavelength.

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0.12 μm hole pattern formation by KrF lithography for Giga bit DRAM

Cited by 8 publications

References 2 publications

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Nanofabrication with deep-ultraviolet lithography and resolution enhancements

Red-Emitting Organic Electroluminescent Devices with Tetraphenylchlorin Doped into a Hole-Transporting Material

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