0.12 μm raised gate/source/drain epitaxial channel NMOS technology

Abstract

ABSTRUCTWe introduce a 0.12 pn nMOS technology with multiVth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 pn nMOS. This device has high f T and low noise figure which are very important for RF analog circuit design. High IdriveDoff ratio for drain current was also realized. INTRUDUCTIONDownsizing of CMOS is a very useful way to improve RF characteristics of MOSFETs. In order to obtain high RF performance under low supply voltage requested by scaled CMOS, extremely low threshold voltage is necessary, as well as low gate electrode resistance.To realize extremely low threshold voltage with suppressing the short channel effect, undoped epitaxial channel (UEC) MOSFET structure [l] was applied selectively for the RF analog parts while keeping the digital part at the conventional structure, and good results were obtained.For low gate electrode resistance, a raised gate/source/drain (RGSD) structure was evaluated for RF CMOS [2], and significant reduction in the resistance and hence good RF characteristics were confiied. Even though, 0.1 pn gate length MOSFETs were demonstrated in the case of [2], both structures basically made use of 0.18 pm device structure and process parameters. In this work, we have combined both the UEC and RGSD structures and developed a 0.12 pn gate length mixed analog digital RF nMOS technology almost compatible with 1997 SIA roadmap 0.12 ptn gate length logic and mixed analog CMOS technology (so-called 0.15 pn technology generation) [3] for the first time. Further better performance acceptable than those of previous works were obtained. SAMPLE FABRICATIONTable I compares device parameters our new 0.12 pn NMOS which is combined UEC and RGSD structures (from now we use the name U R NMOS) with those of the 1997 SIA roadmap. Basically our parameters and structure are compatible to those of the roadmap for 0.12 pm gate length MOSFET (or 0.15 pn technology generation), except that we adopted UEC and RGSD structures. Figs. 1 and 2 show process flow and device cross-section of our UR NMOS. After the isolation formation, thin sacrifice oxide was grown on Si substrate. Then ion-implantation channel doping was carried out. The sacrifice oxide was removed selectively in the analog MOSFET area by using a mask step. Undoped epitaxial Si layer of 30 nm was grown selectively on this area by RP-CVD. SiH2C12 was used during epitaxial growth. The growth temperature was 750 OC. After the growing the selective epitaxial layers, the sacrifice oxide on the digital areas was removed by the etching of the entire region without masking. Then, the gate oxide is grown. The temperature and time of gate oxide formation in dry O2 atmosphere were 800 O C and 4 minutes, respectively. The thickness of gate oxide was 2.5 nm, which value is used for the supply voltage of 1.2 V. This thickness was determined by TEM photograph observation. The phosphorus ...

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

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Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

“…Recently, a number of new transistor structures, such as asymmetric channel structure, epitaxial channel MOSFETs etc. were proposed [7][8][9] to get rid of these negative effects eliminating halo implants. The impact of halo angle on hot carrier reliability was also reported in literature [10,11].…”

Low frequency drain current flicker noise model for pocket implanted nano scale n-MOSFET

“…Already few papers have been published focusing on the degradation of drain current flicker noise due to pocket implantation in MOSFETs [9][10][11][12][13][14][15]. New pocket structures, such as, single pocket, asymmetric channel structure, [9,11] and epitaxial channel MOSFETs [12,13], were proposed to reduce the drain current flicker noise by elimination of pocket implantation. The low frequency noise in pocket implanted MOSFETs may result from additional oxide trap creation due to pocket implantation [13], but this was also not supported by the experiment [14].…”