0.25 μm merged bulk DRAM and SOI logic using patterned SOI

Abstract

The successful fabrication of commodity 64 Mb DRAM chips and logic device and circuits on patterned SO1 wafers is reported for the first time. The effect of SIMOX implantation and annealing on DRAMS in patterned SO1 wafers is studied.Excellent yields and comparable performance of DRAM in bulk regions of the patterned SO1 wafers are observed. The logic devices in the adjacent SO1 area of the patterned wafer show the expected enhanced drive current. This approach enables SO1 based embedded DRAM.

SOI technology for the GHz era

“…EDRAM on SOI is to use patterned SOI: Build the DRAM cells on bulk Si and all of the other circuits on SOI [26]. Figure 14 shows an implementation of patterned SOI [27].…”

“…In fact, we have built EDRAM macros on such films. Figure 15 shows retention-time (time for the first memory failure to retain data beyond specific value) plots of array diagnostic monitors (ADMs) produced on a 524Kb macro using bulk and patterned SOI [26]. (The ADM is a macro that specifically tests EDRAM cell functionality in an array environment and its retention characteristics.)…”