0.2mW 70Fs<sub>rms</sub>-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Zhang, Haosheng; Narayanan, Aravind Tharayil; Herdian, Hans; Liu, Bangan; Wang, Yun; Shirane, Atsushi; Okada, Kei

doi:10.23919/vlsic.2019.8778059

Cited by 17 publications

(13 citation statements)

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“…7(a)-(c) for different N's and β's. The predicted analytical results by (22) [i.e., black curves in Fig. 7(a)-(c)] have a near perfect agreement with the simulation results, thus demonstrating its efficacy.…”

Section: F Numerical Verificationsupporting

confidence: 55%

“…The in-band PN of ( 22) could be dominated by N 2 L ref when f → 0. Interestingly, neglecting the third term in (22) and assuming…”

Section: E Multirate Timestamp Model Of Csl (Or Ilo)mentioning

confidence: 99%

“…First, assuming L ref = 0, we verify the second and third terms of (22). For example, considering a 10-GHz oscillator with L osc @10 MHz = 10 −140/10 rad 2 /Hz in a free-running mode [see (15)] being charge-sharing locked with a clean reference, its PN plots are shown in Fig.…”

Section: F Numerical Verificationmentioning

confidence: 99%

“…Yoo et al [17] and Kim et al [20] proposed a low-power phase-sampling-based FTL with an assumption that, in a quadrature VCO (Q-VCO), the phase of Q-VCO's Q-component could record the frequency deviation with the normal injection into its in-phase (I)-component (exploiting a natural delay for the I-component's injection affecting its Q-component). A similar idea was extended to a differential VCO in [22]. Irrespective of the choice of analog FTL (or FLL), the analog loop filter usually occupies a large area [6], [7], [17], resulting in high costs in advanced CMOS.…”

mentioning

confidence: 99%

“…Surprisingly, a general PN theory in IL is still missing [24]- [26]. The conventional s-or z-domain (at reference rate) analyzing techniques [16], [19], [26], [27] model ILOs in the same manner as in the conventional type-I PLLs with a single integrating pole [28], but they fail to predict the ILO's special PN phenomena, such as the extremely strong suppressing ability of the oscillator's PN and the PN folding effect resulting in the ILO's PN being 3 dB higher outside of the "loop" bandwidth than when the oscillator is free-running [22], [23], [29]- [31]. Combining a discrete-time model with a continuous-time zero-order hold (ZOH) function, Ye et al [13] derived a pioneering but provisional PN model of an ILO.…”

mentioning

confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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Section: F Numerical Verificationsupporting

confidence: 55%

“…The in-band PN of ( 22) could be dominated by N 2 L ref when f → 0. Interestingly, neglecting the third term in (22) and assuming…”

Section: E Multirate Timestamp Model Of Csl (Or Ilo)mentioning

confidence: 99%

Section: F Numerical Verificationmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoM_ref

2021

2021 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Bae

2022

IEEE Access

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A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started breaking. Also, it misses performance impacts from some other important factors other than the jitter and the power. As a result, it is expected that the performance comparison with the conventional FOM is not fair enough for some cases. This work reviews the state-of-the-art PLL design techniques and investigates how those techniques conflict with the assumptions of the conventional FOM. In addition, alternate FOMs which complement the conventional FOM are discussed. To capture complex cross-correlation between various factors, the proposed methodology is to find a correlation between the conventional FOM and other factors from extensive performance surveys, along with quantitative analyses.

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0.2mW 70Fs_rms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Cited by 17 publications

References 0 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoM_ref

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

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0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Cited by 17 publications

References 0 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

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Product

Resources

About

0.2mW 70Fs_rms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoM_ref