0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

Abstract

An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3-4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm 2 .

A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process

“…Using a single-ended input clock signal, two 50 GHz cables, and two 50 GHz probes, the ECL divider was measured to operate from 1 GHz to 62 GHz. For input frequencies near the input referred self-oscillation frequency (SOF) [11,24,28,29], the divider operates at the lowest input power level, which equals -70 dBm. The output power range of the divider is from -6.3 dBm to 0.5 dBm.…”