0.8 mW 1.1–5.6 GHz dual-modulus prescaler based on multi-phase quasi-differential locking divider

Yu, Xiaopeng; Lim, Wei Meng; Lu, Zhenghao; Gu, Jianlan; Liu, Y.; Kiat-Seng, Y.

doi:10.1049/el.2010.8825

Cited by 5 publications

(8 citation statements)

References 2 publications

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“…The maximum operating frequency of the prescaler was measured at 6.2 GHz, whereas the minimum operating frequency was 4.8 GHz with an injected input power of 3 dBm. Instead of using a lower supply voltage as in [1,2,4], the standard supply voltage of 1.8 V for 0.18 μm CMOS technology was used since most of the circuits were digital blocks. The 4/5 dual-modulus prescaler dissipates 0.5 mW when operated at 6.2 GHz.…”

Section: Implementation Of Programmable Delay In Ilfdmentioning

confidence: 99%

“…Introduction: The high-speed frequency divider is a key block in frequency synthesisers for wireless communications [1][2][3][4]. The dualmodulus or multi-modulus prescaler is the most challenging block among all kinds of frequency divider designs for its highest operating frequency in the system while variable division ratios are desired.…”

mentioning

confidence: 99%

“…The injection-locked frequency divider (ILFD), owing to its ultra-high operating frequency and low power consumption, has been regarded as an ideal candidate in high-speed frequency dividers. Several ILFDs with variable division ratios have been demonstrated in the recent literature [1][2][3][4]. However, the delay of the oscillator core in these dividers should be properly adjusted to obtain different division ratios, where proper sizing of devices or delay lines is needed.…”

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confidence: 99%

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6.2 GHz 0.5 mW two‐dimensional oscillator array‐based injection‐locked frequency divider in 0.18 μm CMOS

Xiong

Lim³

et al. 2015

Electron. lett.

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A new two-dimensional oscillator array-based injection-locked frequency divider is proposed. Instead of using the conventional analogue tuning technique or the one-dimensional delay chain, a two-dimensional array is implemented to digitally and precisely control the total delay in the oscillator core. This makes it possible to achieve a programmable delay, hence attaining potential programmable division ratios for the injection-locked divider. Fabricated in a standard 0.18 μm CMOS technology, a prototype chip, namely a divide-by-4/5 prescaler using this technique, is able to work up to 6.2 GHz with 0.5 mW power consumption from a 1.8 V supply voltage.

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Section: Implementation Of Programmable Delay In Ilfdmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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6.2 GHz 0.5 mW two‐dimensional oscillator array‐based injection‐locked frequency divider in 0.18 μm CMOS

Xiong

Lim³

et al. 2015

Electron. lett.

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“…It is usually implemented with a digital circuit which consumes quite a large power at the gigahertz range [1]. The injection-locked frequency divider (ILFD), which achieves a higher operating frequency with lower power consumption, is a promising solution for high-speed applications [2,3]. Nevertheless, the ILFD is conventionally of a fixed division ratio, which limits its usage in today's VLSI systems.…”

mentioning

confidence: 99%

“…Nevertheless, the ILFD is conventionally of a fixed division ratio, which limits its usage in today's VLSI systems. Several ILFDs have been proposed recently to overcome this issue [3]. For example, by proper sizing of transistors in the oscillator core, two self-resonant frequencies at dual-modulus operations are designed to host dual division ratios [3].…”

mentioning

confidence: 99%

0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique

Lim

et al. 2013

Electron. lett.

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A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phaselocked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a widerange operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.Introduction: The dual-modulus prescaler is widely utilised in the frequency divider for phase-locked frequency synthesisers where programmable divisions are needed. It is usually implemented with a digital circuit which consumes quite a large power at the gigahertz range [1]. The injection-locked frequency divider (ILFD), which achieves a higher operating frequency with lower power consumption, is a promising solution for high-speed applications [2,3]. Nevertheless, the ILFD is conventionally of a fixed division ratio, which limits its usage in today's VLSI systems. Several ILFDs have been proposed recently to overcome this issue [3]. For example, by proper sizing of transistors in the oscillator core, two self-resonant frequencies at dual-modulus operations are designed to host dual division ratios [3]. Such a solution is quite simple but not robust against potential process variations since the switching of self-resonant frequency depends heavily on the transistor's parasitic capacitance. The heterodyne phase-locking technique, as proposed in [4], is able to provide flexible division ratios. However, it has a large silicon area and long settling time. In this Letter, a new heterodyne phase-locking divider is proposed. A good compromise among robustness, operating range, power consumption, and silicon area is achieved.

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A dynamic current mode design approach of 2/3 prescaler for phase locked loop application

Saw¹,

Nanda

Laskar

et al. 2021

Analog Integr Circ Sig Process

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Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be -147.001 dBc/Hz and -181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.

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0.8 mW 1.1–5.6 GHz dual-modulus prescaler based on multi-phase quasi-differential locking divider

Cited by 5 publications

References 2 publications

6.2 GHz 0.5 mW two‐dimensional oscillator array‐based injection‐locked frequency divider in 0.18 μm CMOS

6.2 GHz 0.5 mW two‐dimensional oscillator array‐based injection‐locked frequency divider in 0.18 μm CMOS

0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique

A dynamic current mode design approach of 2/3 prescaler for phase locked loop application

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