1/5 power reduction by global optimization based on fine-grained body biasing

Nakamura, Yuya; Levacq, David; Xiao, Limin; Minakawa, T.; Niiyama, Taro; Takamiya, Makoto; Sakurai, Takayasu

doi:10.1109/cicc.2008.4672143

Cited by 9 publications

(6 citation statements)

References 3 publications

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“…The main limitation of this work is that Vdd assignment is done at design time, i.e., statically. Within the same category, [17] introduces a row-based scheme for ultra-fine grain body-biasing. Differently from [16], the layout is partitioned into equally sized bunches of rows.…”

Section: Within the Core Power Managementmentioning

confidence: 99%

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

Peluso

Rizzo

Calimera

et al. 2017

IFIP Advances in Information and Communication Technology

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DVFS is the de-facto standard for low energy Multi-Processor SoCs. It is based on the simple, yet efficient principle of lowering the supply voltage (Vdd) to the minimum threshold that satisfies the frequency constraint (f clk) required by the actual workload. An ideal-DVFS deals with the availability of on-chip high resolution voltage regulators that can deliver the supply voltage with a fine step resolution, a design option that is too costly. While previous research focused on alternative solutions that can achieve, or at least get close to, the efficiency of ideal-DVFS while using a discrete set of supply voltages, this work introduces Ultra-Fine Grain Vdd-Hopping (FINE-VH), a practical methodology that brings DVFS beyond its theoretical limit. FINE-VH leverages the working principle of Vdd-Hopping applied withinthe-core by means of a layout-assisted, level-shifter free, dynamic dual-Vdd control strategy in which leakage currents are minimized through an optimal timing-driven poly-bias assignment procedure. We propose a dedicated back-end flow that guarantees design convergence with minimum area/delay overhead for a cutting-edge industrial Fully-Depleted SOI (FDSOI) CMOS technology at 28 nm. Experimental results demonstrate FINE-VH allows substantial power savings w.r.t. coarse-grain (i) ideal-DVFS, (ii) Vdd-Hopping, (iii) Vdd-Dithering, when applied on the design of a RISC-V architecture. A quantitative analysis provides an accurate assessment of both savings and overheads while exploring different design options and different voltage settings.

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Section: Within the Core Power Managementmentioning

confidence: 99%

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

Peluso

Rizzo

Calimera

et al. 2017

IFIP Advances in Information and Communication Technology

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show abstract

“…The main limitation is that Vdd assignment is done at design time, i.e., statically. Within the same category, [11] introduces a rowbased scheme for ultra-fine grain body-biasing. Differently from [10], the layout is partitioned into equally sized bunches of rows.Such a structure is more flexible as it enables dynamic body-biasing scheduling for post-silicon PV compensation.…”

Section: Previous Work On Ultra-fine Grain Schemesmentioning

confidence: 99%

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs

Peluso

Calimera

Macii

et al. 2016

2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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This paper introduces Ultra-Fine Grain Vdd-Hopping (FINE-VH), an extension of Dynamic Voltage-Frequency Scaling (DVFS) for energy efficient Multi-Processor SoCs (MPSoCs). The proposed technique leverages the working principle of Vdd-Hopping applied at ultra-fine granularity, i.e., within the core, by means of a layout-assisted, level-shifter free, dynamic dual-Vdd control strategy where leakage currents are minimized through an optimal timing-driven poly-bias assignment procedure. A dedicated back-end flow implementing FINE-VH has been devised such to guarantee design convergence with minimum area/delay overhead; such a tool is centered for an industrial Fully-Depleted SOI (FDSOI) CMOS technology at 28nm. Simulation results, conducted on an open-source RISC-V core (the RI5CY core) belonging to an MPSoC platform (the PULP platform), demonstrate FINE-VH allows substantial power savings w.r.t. coarse-grain ideal-DVFS (best-case 32.6%, average 22.9%) and state-of-the-art Vdd-Hopping (best-case 60.1%, average 42.5%) and Vdd-Dithering (best-case 38.3%, average 26.8%).

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“…1, increasing the number of stages in ring oscillators degrades their operation at low voltages. To resolve this issue, some postfabrication approaches, including individual body-biasing, have been proposed, (2) although such approaches increase the cost of production, making them impractical. The difficulty of lowering the supply voltage inhibits the development of low-voltage applications such as devices powered by biofuel cells.…”

Section: Introductionmentioning

confidence: 99%

“…(1) Four ring oscillators and the OR-gate have a common power-supply voltage, eliminating the need for a cost-hungry multi-supply/body-voltage approach. (2) As a typical example, we have determined the number of ring oscillators to be four. The number of ring oscillators can be determined by considering the trade-off between effectiveness and area/power overhead.…”

Section: Introductionmentioning

confidence: 99%

Design and Verification of Stochastic Oscillator Using Multiple Ring Oscillators and OR-gate for Low-voltage Operation in 65 nm CMOS

Murakami¹,

Hayashi²,

Arata³

et al. 2020

Sensors and Materials

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In this paper, we present a stochastic oscillator comprising multiple ring oscillators and an OR-gate intended for low-supply-voltage operation for the first time. To achieve low-supply-voltage operation under a wide range of process variations, multiple ring oscillators are employed. By using an OR-gate, the ring oscillator with the lowest voltage can be utilized, which was confirmed by SPICE simulations. The prototype is fabricated using 65 nm CMOS technology. Measurement results show the effectiveness of the proposed oscillator.

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1/5 power reduction by global optimization based on fine-grained body biasing

Cited by 9 publications

References 3 publications

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs

Design and Verification of Stochastic Oscillator Using Multiple Ring Oscillators and OR-gate for Low-voltage Operation in 65 nm CMOS

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