1.58 GHz Low Noise Amplifier Design and Verification in 130 nm CMOS Technology

Surin, Igor K.; Antonov, Andrey A.; Shlemin, Dmitry L.

doi:10.1109/edm.2018.8434941

2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM) 2018

DOI: 10.1109/edm.2018.8434941

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1.58 GHz Low Noise Amplifier Design and Verification in 130 nm CMOS Technology

Igor K. Surin¹,

Andrey A. Antonov²,

Dmitry L. Shlemin³

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Cited by 2 publications

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An Interface Model of the Interconnection Between Integrated Circuit Chip Die and Printed Circuit Board

Antonov¹,

Surin²

2018

2018 19th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM)

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1.58 GHz Low Noise Amplifier Design and Verification in 130 nm CMOS Technology

Cited by 2 publications

References 9 publications

An Interface Model of the Interconnection Between Integrated Circuit Chip Die and Printed Circuit Board

An Interface Model of the Interconnection Between Integrated Circuit Chip Die and Printed Circuit Board

A High Gain 450/900 MHz Dual Band Low Noise Amplifier for IoT and LTE Low-Band Receivers

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