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put voltage modulation by the clock frequency takes place. The maximum clock frequency we have reached is about 5 Mhz and this fact is explained by the limited op amp bandwidth, nevertheless, it is not bad for the 3-um process array-based design.For the 10-bit DAC design we have chosen a two-stage configuration employing a segmented approach similar to that proposed in /5/. The area efficiency of this configuration is much better in comparison with the classical one-stage codlgydon, for example, in the case of 10-bit DAC it was required about 100 unit capacitors for our DAC and for the classical one-stage configuration it is necessary to have more than 2000 unit capacitors. Of course, there are many of more areaeffective DAC configurations, for example, an algorithmic DAC, but all these configurations are very slow for 1 O-bit resolution. The configuration considered is a sufficiently good compromise between area efficiency and speed. Moreover, the configuration considered guarantees DAC monotony even if appreciable deviations of capacitor capacities take place. To decrease the influence of op amp noise and offset voltages upon the DAC resolution the autozeroing and double-correlated sampling were introduced in the DAC configuration. The experimental measurements of the DAC show that it ensures the 10-bit resolution. Thus, the analog-digital mixed-mode semicustom gate array-based design is proven to be a reasonable effective way of high-performance mixed-mode ASIC design using the SC technique.The grade of performance obtained through the way considered is high enough for many mixed applications and close to the full-custom design.. Summary.The switched-capacitor and switched-current techniques are known to be the basic means of analog-digital mixed-mode ASIC design. As it was shown in this paper, the semicustom-arraybased SC design allows to reach close-to-full-custom performance but its main drawback is inflexibility due to the hard array architecture providing for special fixed analog fields. The functional ability (up to 42 op amps, more than 250 pF and almost 2 Mom of overall capacitance and resistance respectively and 1500 logic gates) of the array considered, nevertheless, is high enough. To overcome the drawback involved an analog-digital symbolic design methodology is supposed to use in future work taking into account the results considered in this paper. . 5. Lakshmikumar K.R. et al. A baseband codec for digital cellular telephony. // EEE journal Delft. -1986.-p.80-81. cuits. // EEE transactions on circuits and systems.