1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades

Abstract

The radiation tolerance of 65 nm bulk CMOS devices was investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 1 Grad. Irradiation tests were performed at room temperature (25 • C) as well as at low temperature (−15 • C). The implications on the DC performance of n and p channel transistors are presented. For small size devices, a strong performance degradation is observed from a dose of 100 Mrad. Irradiations made at room temperature up to 1 Grad show a complete drive loss in PMOS devices, due to decreasing transconductance. When the irradiation is conducted at −15 • C, the devices show less radiation damage. Annealing helps recovering a small part of the drive capabilities of the small size devices, but the threshold voltage shift is still high and might compromise the operation in some digital applications.

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity

“…In a second step, annealing at 100 • C was performed and measured after 4 and 24 hours. The annealing was performed with the circuit biased in normal operating conditions, which has the most damaging effect [21]. The second sample was irradiated up to 600 Mrad and measured after 24 hours room temperature annealing and 24 hours annealing at 100…”

“…Compared to the LC-oscillator, a large annealing effect is observed. According to [21], this is due to the short-channel devices in the cells for which the effects are triggered after high-temperature annealing. The large variation in tuning characteristics caused the PLL to be unable to lock after being irradiated to 600 Mrad since the oscillator could no longer run at 2.56 GHz.…”

Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

“…X-rays provide a good way to compare old with new data, even though very long exposure times are needed to reach TID levels up to 1 Grad: a review of the results can be found in [16]. The results show significant degradation above 100 Mrad, particularly in core minimum size pMOSFETs.…”

65 nm Technology for HEP: Status and Perspective

“…Simulations show that its pixel detectors will integrate a fluence (1 MeV neutron equivalent) of about 10 16 n/cm 2 and a Total Ionizing Dose (TID) of 10 MGy (1 Grad). The radiation damage on the proposed 65 nm technology, due to both total dose and single event effects, has been studied by the RD53 Radiation Working Group [3]. Tests were done on single transistors with different geometries.…”