The radiation tolerance of 65 nm bulk CMOS devices was investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 1 Grad. Irradiation tests were performed at room temperature (25 • C) as well as at low temperature (−15 • C). The implications on the DC performance of n and p channel transistors are presented. For small size devices, a strong performance degradation is observed from a dose of 100 Mrad. Irradiations made at room temperature up to 1 Grad show a complete drive loss in PMOS devices, due to decreasing transconductance. When the irradiation is conducted at −15 • C, the devices show less radiation damage. Annealing helps recovering a small part of the drive capabilities of the small size devices, but the threshold voltage shift is still high and might compromise the operation in some digital applications.

a b s t r a c t High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq =cm 2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

Keywords:High-voltage pixel detector Smart diode array HVMAPS High-voltage CMOS technology Capacitive coupled pixel detector CCPD a b s t r a c tThe high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the highluminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

The XPAD3 is the third generation of a single photon counting chip developed in collaboration by SOLEIL Synchrotron, the Institut Néel and the Centre de Physique de Particules de Marseille (CPPM). The chip contains 9600 pixels of 130 µm side and a counting electronic chain with an adjustable low level threshold in each pixel. Imaging and detection performance (detective quantum efficiency, modulation transfer function and energy resolution) of the XPAD3 detectors hybridized with Si and CdTe sensors have been evaluated and compared using monochromatic synchrotron X-rays beam. A second version of the chip, optimized for pump-probe experiments, has been realized and successfully tested. Three 7.3 cm x 12.5 cm Si-XPAD3 imagers, composed of 8 silicon modules (7 chips per module) and one 2.1 cm x 3.1 cm CdTe-XPAD3 imager (4 chips) have been constructed and successfully used for synchrotron diffraction experiments and biomedical imaging.