10-bit switched-current digital-to-analogue converter

Abstract

The design of a 10-bit switched-current digital-to-analogue (D/A) converter is presented. A combined-input algorithm is adopted to reduce both architecture and power dissipation. The proposed D/A converter is implemented with a standard 0.35 mm CMOS process technology. The chip occupies an area of 0.35 mm 2 and consumes a small power of 26.1 mW with speed-up to 31.25 Msamples/s.

High speed switched-current memory cell with very low offset and charge injection errors

“…Most of them generate an extra current error at output node which contains signal dependent part, offset or both of them. These techniques are mostly complicated due to containing complex structure and clock circuit [8][9][10][11].…”

“…To minimize the error, several techniques have been proposed. Some of them are based on generating additional error currents to cancel the original one at the output [8][9][10][11]. Attenuation, algorithmic, adaptive and zero-voltage switching are the other presented techniques but for achieving a complete cancelation (only in theory), complicated circuit and/or clock scheme techniques are unavoidable.…”

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“…Since transistors M0, M1 and M2 are connected serially and with the gates connected to their own drains. They all operate in the saturation region [1].…”

“…Digital-to-analog (D/A) converters and analog-to-digital (A/D) converters with high performance are in high demand for many applications, such as scanning graphic systems computer systems and digital TV, etc [1]. In data communication systems, when signals are transmitted from one system to another system, they are often handled in a digital manner.…”