10-ps Resolution hybrid time to digital converter in a 0.18 &amp;#x03BC;m CMOS technology

Malass, Imane; Uhring, Wilfried; Normand, Jean-Pierre Le; Dumas, Norbert; Dadouche, Foudil

doi:10.1109/newcas.2014.6933995

Cited by 6 publications

(3 citation statements)

References 12 publications

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“…The residual jitter obtained between these two signals using this setup was evaluated by means of a "LeCroy wave master 13Zi" oscilloscope and it was found to be less than 7 ps rms. We introduced a hybrid TDC architecture capable of achieving good time resolutions without the need to use extremely high clock frequencies or exceptionally long DLL delay lines, and with reasonable power consumption and silicon area occupation [10]. The hybrid TDC architecture was used to realize a TDC array incorporating 8 independent TSU sharing a DLL, a coarse counter and a data acquisition unit in a 180 nm standard CMOS technology (Figure .…”

Section: Characterisation Resultsmentioning

confidence: 99%

“…Alternatively, digital DLL-based TDCs offer a reasonable dynamic range but it comes with the price of a more complex design, high power consumption and a large chip area. We recently introduced a hybrid TDC design [10] which makes use of the analog TDC and digital TDC concepts to achieve a high adjustable time resolution that could reach 10 ps and a flexible large dynamic range with a maximum value of 10μs. In this paper, we report on the design and characterization of the proposed hybrid TDC implemented in a 180 nm Standard CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

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A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Malass

Uhring

Normand

et al. 2017

2017 29th International Conference on Microelectronics (ICM)

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This paper presents the simulations and characterizations results of a hybrid Time to Digital Converter (TDC) fabricated in 180 nm standard CMOS. The design combines the traditional Analog Time to Amplitude Converter (TAC) and Digital TDC techniques to obtain a high adjustable time precision. These approach leads to a 3 bits enhancement of the least significant bit resolution (LSB) for the proposed design. The characterization results showed a time precision of 10 ps with an estimated INL of 5.6 ps rms for a 2.5 ns reference period clock and a 32 cells delay line loop.

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Section: Characterisation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Malass

Uhring

Normand

et al. 2017

2017 29th International Conference on Microelectronics (ICM)

Self Cite

View full text Add to dashboard Cite

show abstract

“…The design of such sensors requires taking into account several aspects [3,4], such as the structure of the SPAD itself, the physical technology of the components, and the associated electronic circuits. The last point ranges from simple detection and quenching systems to more sophisticated ones incorporating photon counting, or integrating the ability to measure temporal resolution [11,12] and whether they integrate memory or not. These electronics can be built as close as possible to the SPAD cell or shifted to the end of the SPAD array.…”

Section: Introductionmentioning

confidence: 99%

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

Aguénounon

Razavinejad

Schell

et al. 2021

Sensors

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The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.

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A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology

Kong

Siek

Kok

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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A high resolution Vernier Ring Time-to-digital Converter is presented in this paper. Body bias is applied to its delay cells to obtain a finer delay difference between two delay chains. The delay cells and arbiters are implemented in a ring structure, thus allowing a large input time interval to be measured. The digital circuit nature of this converter is also attractive for low power and small area design. The simulation results reveal a 3 ps resolution, a -0.22/0.11 LSB differential nonlinearity (DNL) and a 9-bit range. The prototype chip is fabricated in 65 nm CMOS process consuming 0.44 mW with a 1.2 V power supply and occupies an area of 0.014 mm 2 . I.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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10-ps Resolution hybrid time to digital converter in a 0.18 μm CMOS technology

Cited by 6 publications

References 12 publications

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

A hybrid time to digital converter based on digital delay locked loop and analog time to amplitude converter

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology

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