12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis

Song, Taejoong; Kim, Hoonki; Rim, Woojin; Kim, Yong-Ho; Park, Sunghyun; Park, Changnam; Hong, Minsun; Yang, Gi-Yong; Do, Jeongho; Lim, Jinyoung; Lee, Seungyoung; Kim, Ingyum; Baek, Sanghoon; Jung, Jonghoon; Ha, Daewon; Jang, Hyungsoon; Lee, Tae-Jung; Park, Chul‐Hong; Kwon, Boksoon; Jung, Hoeryong; Cho, Sungwee; Choo, Yongjae; Choi, Jae-Seung

doi:10.1109/isscc.2017.7870334

Cited by 15 publications

(6 citation statements)

References 3 publications

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“…I PGL and I PGR are the currents flowing through the PGL and PGR during the write operation, respectively. The V CS is determined by the charge sharing between the floated CV DD and BL precharged to half-V DD by the CSBP, as shown in Equation (10). When the CSWD is used with the conventional BP, the V CS is 0 since the voltages of precharged BL and CV DD are the same as V DD .…”

Section: A Structure and Operationmentioning

confidence: 99%

“…1(b). For improving writability, the negative bitline (NBL) [5], [7], [10], [12], [14]- [16], transient cell supply collapse (TVC) [4], [8], [13]- [17], transient cell ground bump (TGB) [18]- [20], or wordline overdrive (WLOD) WA [9], [12], [21], [22] is used. Although the various RA and WA techniques reduce the V MIN , reducing the energy consumed in the assist circuit is still challenging.…”

Section: Introductionmentioning

confidence: 99%

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Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Kim

Jung

2021

IEEE Access

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This paper proposes a bitline charge sharing suppressed bitline read assist (BCS RA) and a cell supply collapse write assist (BCS WA). The proposed BCS RA suppresses the bitline (BL) voltage to half of the supply voltage (V DD ) using the charge sharing BL precharger for improving read stability and energy efficiency. In the proposed BCS WA, the charge on cell V DD (CV DD ) is shared with that on the BL precharged to half-V DD by the charge sharing write driver, which causes the collapse in CV DD . In cells with poor writability, CV DD can be collapsed more by the self-collapse paths when the write operation is performed. Thus, the BCS WA improves writability and reduces write energy consumption. The simulation results using 22-nm FinFET technology show that static random access memory (SRAM) using BCS RA and WA consumes much less read and write energy than SRAMs using state-of-the-art assists while achieving a comparable minimum operating V DD to SRAMs using state-of-the-art assists. Even compared to the SRAM without assists, the read and write energy consumption is reduced by 31% and 26%, respectively. INDEX TERMSFinFET SRAM, read assist, write assist, V MIN improvement, energy-efficient read and write operations.

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Section: A Structure and Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Kim

Jung

2021

IEEE Access

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“…The fact that the fabrication technologies for semiconductor devices continue to progress is also beneficial to charge qubits. Now, the cell size of advanced 2D NAND flash memory [36][37][38] is less than 15 nm 39,40 , and the transistor size are entering into the quantum region below 7 nm [41][42][43] . The disadvantage of the charge qubit's short coherence time is expected to be reduced as transistor size decreases.…”

Section: Introductionmentioning

confidence: 99%

“…The fundamental idea is that we will be able to regard a small FG cell in the single-electron region as a charge qubit. The size of the current FG NAND flash memory is 15 nm 39,40 , but it can be shrunk to less than 7 nm [41][42][43] . When the doping concentration of electrons is 5 × 10 18 cm −3 , the number of electrons in a volume of 10×10×30 nm 3 is about 15 and countable.…”

Section: Introductionmentioning

confidence: 99%

Quantum Annealing Machines Based on Semiconductor Nanostructures

2019

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The development of quantum annealing machines (QAMs) based on superconducting qubits has progressed greatly in recent years and these machines are now widely used in both academia and commerce. On the other hand, QAMs based on semiconductor nanostructures such as quantum dots (QDs) appear to be still at the initial elementary research stage because of difficulty in controlling interaction between qubits. In this paper, we review a QAM based on a semiconductor nanostructures such as floating gates (FGs) or QDs from the viewpoint of the integration of qubits. We theoretically propose the use of conventional high-density memories such as NAND flash memories for the QAM rather than construction of a semiconductor qubit system from scratch. A large qubit system will be obtainable as a natural extension of the miniaturization of commercial-grade electronics, although further effort will likely be required to achieve high-quality qubits.

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“…The fundamental idea is that we will be able to regard a small FG cell in the single-electron region as a charge qubit. Now the size of the FG NAND flash memory is 15 nm 17,18 , and the size can shrink to beyond 7 nm [19][20][21] . In the flash memory with 15 nm cell, singleelectron effects can be observed at room temperature 22 .…”

Section: Introductionmentioning

confidence: 99%

Quantum Annealing Machine based on Floating Gate Array

Tanamoto,

Higashi,

Marukame

et al. 2017

Preprint

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12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis

Cited by 15 publications

References 3 publications

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Quantum Annealing Machines Based on Semiconductor Nanostructures

Quantum Annealing Machine based on Floating Gate Array

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