12-4: TFT Integrated Gate Driver with V<sub>TH</sub>Shift Compensable Low-Level Holding Unit

Hu, Zhijin; Wang, Cuicui; Liao, Congwei; Cao, Shijie; Fan, Jin; Zhao, Qiang; Zhang, Shengdong

doi:10.1002/sdtp.10619

Cited by 4 publications

(4 citation statements)

References 16 publications

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“…Fig. 2 (a) shows the conventional V TH extraction method for the pull-down unit using 3T1C (Ta, Tb, Tc, and C1) circuit configuration [15], [16]. In 3T1C conventional circuit structure, Ta, Tb, and Tc are input TFT, V TH compensation TFT, and pull-down TFT, respectively.…”

Section: Proposed Gate Driver Circuit and Operationmentioning

confidence: 99%

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Jung

et al. 2020

IEEE J. Electron Devices Soc.

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This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement-and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the V OUT ripple voltage because the threshold voltage (V TH) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of V TH , depletion mode: negative value of V TH). Many groups proposed the V TH compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the V TH value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the V GS value is 0 V. To solve this problem, we adopted the V TH extraction period only once in one frame time. As a result, our circuit can compensate for V TH of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and V OUT nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the V OUT waveforms are maintained at +28 V (VGH) under the V TH shift conditions from −7 V to +11 V; further, the rising time and falling time are less than 0.62 µs and 0.96 µs, respectively. Based on a 120-Hz ultra-high definition (UHD) graphics (3840×2160) display panel, the proposed circuit has uniform V OUT characteristics compared to previous V TH compensation circuit when V TH changes from −3 V to +11 V. When V TH changes from −4 V to −7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption. INDEX TERMS a-IGZO TFT, gate driver circuit, pull-down unit, enhancement mode, depletion mode, threshold voltage.

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Section: Proposed Gate Driver Circuit and Operationmentioning

confidence: 99%

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Jung

et al. 2020

IEEE J. Electron Devices Soc.

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“…For the large-sized display applications, the lifetime of a-IGZO integrated gate driver is usually not long enough due to the severe degradation of the low-level maintaining (LLM) and pull up (PU) TFTs under the long term electrical stress bias, which mainly embodied as the VTH shift. At present, in order to prolong the lifetime of integrated gate driver, various methods have been reported to suppress the VTH of the LLM TFTs, such as multi pulse signal driving scheme, alternative revised bias, shared dual pull-down units [9][10] . However, very few of these designs were realized with large area manufacturing processes.…”

Section: Introductionmentioning

confidence: 99%

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

Zhou

Shao

et al. 2023

Symp Digest of Tech Papers

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Recently, a‐IGZO TFTs have attracted considerable attention for ultra large‐sized and ultra high‐resolution display due to high mobility and good uniformity. The life‐time of integrated gate driver is mainly determined by the stability of low‐level maintaining and pull‐up TFTs, which always experience severe performance degradation after a long time operation. In this paper, a robust a‐IGZO integrated gate driver with dual lowlevel maintaining units is proposed and fabricated for ultra large‐sized and high resolution TFT‐LCD applications. The simulation and BTS measurement results demonstrate that proposed a‐IGZO gate driver has a large VTH shift margin, which contributes to extended life‐time of circuit operation.

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“…C. W. Liao et al have proposed a simple buffer structure in their SR circuit to suppress the feedthrough effects from the clock signals [ 20 ]. In order to improve the reliability of it, Z. J. Hu et al have designed an amorphous silicon SR circuit with a threshold voltage shift compensable low-level holding unit [ 21 ]. M. Mativenga et al have prepared a simple SR circuit on a plastic substrate [ 22 ].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Shift Register with Dual-Gated Thin-Film Transistors for a 31-Inch 4K AMOLED Display

Rong

Lin

et al. 2022

Micromachines

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In this work, a promising dual-gated thin film transistor (TFT) structure has been proposed and introduced in the shift register (SR)-integrated circuits to reduce the rising time. The threshold voltage can be simultaneously changed by the top gate and the bottom gate in the proposed dual-gated TFTs. When the SR circuits start to export the scan signals in the displays, the driving currents in the SR circuits are increased by switching the working station of driving TFTs from the enhancement characterization to the depletion characterization. Subsequently, the detailed smart spice simulation has been used to study the function of the proposed SR circuits. In the next step, the proposed SR circuits have been fabricated in a G4.5 active-matrix organic light-emitting diode manufacture factory. The simulated and experimental results indicate that the shift register pulses with the full swing amplitude can be obtained in the SR circuits. Moreover, in contrast to the conventional SR circuits employing with the single-gated TFTs, it has been found that the rising time of the output signals can be reduced from 3.75 μs to 1.23 μs in the proposed SR circuits with the dual-gated TFTs, thus exhibiting the significant improvement of the driving force in the proposed SR circuits. Finally, we demonstrated a 31-inch 4K AMOLED display with the proposed SR circuits.

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12-4: TFT Integrated Gate Driver with V_THShift Compensable Low-Level Holding Unit

Cited by 4 publications

References 16 publications

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

High-Speed Shift Register with Dual-Gated Thin-Film Transistors for a 31-Inch 4K AMOLED Display

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12-4: TFT Integrated Gate Driver with VTHShift Compensable Low-Level Holding Unit

Cited by 4 publications

References 16 publications

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

High-Speed Shift Register with Dual-Gated Thin-Film Transistors for a 31-Inch 4K AMOLED Display

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Product

Resources

About

12-4: TFT Integrated Gate Driver with V_THShift Compensable Low-Level Holding Unit