12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V&lt;inf&gt;DD&lt;/inf&gt;) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V&lt;inf&gt;DD&lt;/inf&gt; between flip-flops and combinational logics

Fuketa,; Hirairi,; Yasufuku,; Takamiya,; Nomura,; Shinohara,; Sakurai,

doi:10.1109/islped.2011.5993630

Cited by 9 publications

(3 citation statements)

References 6 publications

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“…Fig. 5 shows the block diagram of the developed 16-bit IU implemented with popular media processing commands [11]. In this brief, HVFF, which is the proposed circuit design technique for separating the supply voltage of FFs (V DD(FF) ) from that of combinational circuits (V DD(LOGIC) ), is applied to the IU.…”

Section: V Ddmin Of Ffs and Hvffmentioning

confidence: 99%

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Fuketa

Hirairi

Yasufuku

et al. 2013

IEEE Trans. VLSI Syst.

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To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (V DD ) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although V DD scaling can reduce the energy, the minimum operating voltage (V DDmin ) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the V DDmin of FFs is higher than the optimum supply voltage. In HVFF, the V DD of combinational logic gates is reduced below the V DDmin of FFs while keeping the V DD of FFs at their V DDmin . This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.Index Terms-Minimum operating voltage, subthreshold circuits, variations.

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Section: V Ddmin Of Ffs and Hvffmentioning

confidence: 99%

“…1) The sizes of transistors contained in the FF are adjusted to mitigate the contention [2], [12]. 2) The architecture of FFs is changed to eliminate the contention [11]. These techniques, however, result in power and delay penalties as well as additional costs to re-layout the FFs.…”

Section: Introductionmentioning

confidence: 99%

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Fuketa

Hirairi

Yasufuku

et al. 2013

IEEE Trans. VLSI Syst.

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“…In a typical microprocessor, a large number of Flip-Flops (FFs) are used. Therefore, the energy consumed in the FFs occupies a large percentage of the energy consumed in the entire microprocessor [1]. One of the most effective approaches is lowering the supply voltage (V DD ) of FFs since the active energy of the circuit is proportional to V 2 DD .…”

Section: Introductionmentioning

confidence: 99%

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Kamakari

Nishizawa

Ishihara

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (V DDmin ) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.

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A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region

Kamakari

Shiomi

Ishihara

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<inf>DD</inf>) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V<inf>DD</inf> between flip-flops and combinational logics

Cited by 9 publications

References 6 publications

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region

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