2014 IEEE 26th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD) 2014
DOI: 10.1109/ispsd.2014.6855984
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1200V, 25A bi-directional Si DMOS IGBT fabricated with fusion wafer bonding

Abstract: A 1200V, 25A bi-directional silicon DMOS-IGBT has been successfully fabricated using a hydrophobic bonding process at low temperature (400C). With the aid of a glass carrier approach, a flat and clean bonding surface for producing an electrically stable and transparent junction was achieved. The static and dynamic performance with and without back-side gate control are presented and compared.

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Cited by 18 publications
(11 citation statements)
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“…The Dual-Gate Bidirectional IGBT (BD-IGBT or DGIGBT) was first proposed in 1988 by Nakagawa [33]. Fabrication techniques to realise this structure have since been developed and in 2014 a 1200V 25A single-chip dual-gate BD-IGBT was manufactured with a fusion wafer bonding process [34] but fabrication of IGBTs with lower breakdown voltages using this method have resulted non-ideal electrical performance [34].…”
Section: B Rc-igbt With Alternating N/p Buffers (Ab Rc-igbt)mentioning
confidence: 99%
See 1 more Smart Citation
“…The Dual-Gate Bidirectional IGBT (BD-IGBT or DGIGBT) was first proposed in 1988 by Nakagawa [33]. Fabrication techniques to realise this structure have since been developed and in 2014 a 1200V 25A single-chip dual-gate BD-IGBT was manufactured with a fusion wafer bonding process [34] but fabrication of IGBTs with lower breakdown voltages using this method have resulted non-ideal electrical performance [34].…”
Section: B Rc-igbt With Alternating N/p Buffers (Ab Rc-igbt)mentioning
confidence: 99%
“…It is also possible to exhibit MOSFET behaviour when the current is lower than a threshold value IH (typically ~4A/cm 2 ) such that the backside p-well is biased by <0.7V so hole injection does not occur. It is this transition from MOSFET mode to quasi-IGBT mode which exhibits the snapback characteristic in the I-V curve, however, in this operation mode much higher switching speeds can be achieved than in the IGBT mode [35] and higher back-gate voltage reduces the susceptibility of the breakdown voltage and leakage currents with temperature [34]. It has been reported that multifaceted gate drive schemes can be implemented to optimise the switching and on-state losses of the device for various applications [35].…”
Section: B Rc-igbt With Alternating N/p Buffers (Ab Rc-igbt)mentioning
confidence: 99%
“…The processing requirements for the backside are not as stringent as for the frontside since there are no cathode or gate structures. The two halves would be first bonded to glass carriers [13] and then etched to remove the excess wafer required for the SJ trench formation. The wafers are then bonded using a wafer bonding process as demonstrated in [13]- [16].…”
Section: Introductionmentioning
confidence: 99%
“…The two halves would be first bonded to glass carriers [13] and then etched to remove the excess wafer required for the SJ trench formation. The wafers are then bonded using a wafer bonding process as demonstrated in [13]- [16]. These studies have shown that the IGBT performance does not degrade using this technique.…”
Section: Introductionmentioning
confidence: 99%
“…However, the conventional RC-IGBT is not suitable for parallel operation due to its snapback phenomena at forward on-state [2]. To suppress snapback, bi-mode insulated gate transistors [3], RC-IGBTs with floating p-region [4][5][6][7], RC-IGBTs with antiparallel thyristor [8][9][10], and RC-IGBTs with double gates [11][12][13] are proposed. This Letter proposes a new RC-IGBT, i.e.…”
mentioning
confidence: 99%