120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Yang, Hui-Kuo; Chiu, Chao Chang; Lai, Shin Chi; Chen, Jui Lung; Chang, Chih Wei; Meng, Che Hao; Chen, Ke-Horng; Wey, Chin‐Long; Lin, Ying; Lee, Chao Cheng; Lin, Jian Ru; Tsai, Tsung Yen; Luo, Hsin Yu

doi:10.1109/esscirc.2015.7313884

Cited by 5 publications

(17 citation statements)

References 4 publications

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“…In [21], two feedback loops from the level shifter output to input are used to cancel the slew-related influence on the input trigger signals to reach 50V/ns. Finally, Yang et al [7] present a slew rate enhancement technique to achieve 120 V/ns slew rate immunity and a propagation delay of 20 ns. Transient simulation results of basic level shifter in [10]…”

Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

“…The desired increase in switching speed of GaN devices therefore comes with a requirement to ensure that level shifter's slew immunity equals or exceeds the desired slew rate of the switch-node, or else the level-shifted signal V OU T may contain errors. Examples of reported level-shifter slew-rates of are 50V/ns in [2] and [4], 75V/ns in [5], and 120 V/ns in [7].…”

Section: Introductionmentioning

confidence: 99%

“…The move to higher switching speeds also leads to higher switching frequencies, which therefore requires level shifters with reduced propagation delay, ideally sub-ns [2], [3], and reduced low power dissipation per transition. The combination of low delay and high slew immunity is difficult to achieve, for example the 120 V/ns capable level shifter of [7] has a 20 ns propagation delay. For these reasons, new level shifter designs are needed with higher slew immunity and lower propagation delay, to enable commercial gate drivers to that can fully exploit the high switching speed of GaN FETs.…”

Section: Introductionmentioning

confidence: 99%

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A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and subns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/(µmV), which is an 1.7× improvement on the next best reported level shifter for this type of application.

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Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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“…However, these works cannot be used in systems where VSSF slews fast and/or VSSF is negative. AC-LSs with dVSSF/dt slewing immunity are also reported [12][13][14]. The work in [13] presents a dVSSF/dt immunity up to 120 V/ns but has a high delay of 20 ns.…”

Section: Introductionmentioning

confidence: 92%

“…This extends the challenge (Ch4) such that the LS should work even with a large negative potential of the floating ground VSSF. Several level shifters have been proposed [9][10][11][12][13][14][15][16][17], which can be divided into two main categories: active-coupled LS (AC-LS) [9][10][11][12][13][14][15] and capacitive-coupled LS (CC-LS) [16][17]. AC-LSs presented in [9][10][11] achieve a delay of 3 ns, 2.03 ns and 1.3 ns, respectively.…”

Section: Introductionmentioning

confidence: 99%

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

Nguyen

Alameh

et al. 2021

IEEE Trans. Circuits Syst. II

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This paper presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitivecoupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 µm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of dVSSF/dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM 1 and FoM 2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

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The High-Voltage Level Shifter with dV/dt noises Shielding

Zhou

Zhang

2022

Preprint

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This paper proposes a HV (high-voltage) level shifter to shield the dV/dt noise. The main mechanism is to determine whether there is dV/dt noise through signal changes. When there is the dV/dt noise, the proposed level shifter’s output is locked by the dV/dt noise shielding circuit. So, the proposed level shifter has infinite dV/dt immunity, which is not affected by the supply voltage, and processes. In normal operation, the proposed level shifter can still maintain high response speed by using the auxiliary circuit. Therefore, the proposed HV level shifter cannot only realize dV/dt noise shielding, but also have a fast response speed. In the 0.5µm BCD process, the proposed level shifter is simulated, realizing the ±250V/ns dV/dt noises shielding function and less than 1.5ns delay time under the 400V HV power supply.

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120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Cited by 5 publications

References 4 publications

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers

The High-Voltage Level Shifter with dV/dt noises Shielding

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