13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

Hirairi, Koji; Okuma, Yasuyuki; Fuketa, Hiroshi; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu

doi:10.1109/isscc.2012.6177102

Cited by 30 publications

(10 citation statements)

References 3 publications

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“…Some methods can be used to reduce the overhead (e.g., [16]), but with a loss in accuracy. Better monitor designs, e.g., [17], can also reduce the overhead, but are still fundamentally limited by the large number of monitors requited.…”

Section: Introductionmentioning

confidence: 99%

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology

Lai

Chandra

Aitken

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually incurs significant overhead. We observe that most existing slack monitoring methods focus exclusively on monitoring path endpoints, which is not cost efficient from power and area perspectives.In this paper, we first propose SlackProbe methodology, which inserts timing slack monitors like "probes" at a selected set of nets, including intermediate nets along critical paths. SlackProbe can be used to detect impending delay failures due to various reasons (process variations, ambient fluctuations, circuit aging, etc.) and can be used with various preventive actions (e.g., voltage/frequency scaling, clock stretching/time borrowing, etc.). Then we perform thorough analysis of the potential benefits and caveats of SlackProbe over conventional approaches in terms of number of monitors required, monitoring efficiency and observability, delay margin, and design perturbation. Experimental results on commercial processors show that with 5% extra timing margin, SlackProbe can reduce the number of monitors by 12-16X as compared to the number of monitors inserted at path ending pins. SlackProbe can also improve the monitoring efficiency by up to 1.9X and improve the monitoring observability by up to 32%, as compared to endpoint monitoring.

show abstract

Section: Introductionmentioning

confidence: 99%

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology

Lai

Chandra

Aitken

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Some methods can be used to This work is supported in part by NSF Variability Expedition grant CCF-1029030 978-3-9815370-0-0/DATE13/ c 2013 EDAA reduce the overhead (e.g. [16]), but with a loss in accuracy. We observe that most of existing methods exclusively focus on monitoring path endpoints (i.e.…”

Section: Introductionmentioning

confidence: 99%

SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology

Lai¹,

Chandra

Aitken

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually incurs significant overhead. We observe that most existing slack monitoring methods exclusively focus on monitoring path ending registers, which is not cost efficient from power and area perspectives.In this paper, we propose SlackProbe methodology, which inserts timing slack monitors like "probes" at a selected set of nets, including intermediate nets along critical paths. SlackProbe can significantly reduce the total number of monitors required at the cost of some additional delay margin. It can be used to detect impending delay failures due to various reasons (process variations, ambient fluctuations, circuit aging, etc.) and can be used with various preventive actions (e.g. voltage/frequency scaling, clock stretching/time borrowing, etc.). Though we focus on monitor selection in this work, we give an example of using SlackProbe with adaptive voltage scaling.Experimental results on commercial processors show that with 5% more timing margin, SlackProbe can reduce the number of monitors by 15-18X as compared to the number of monitors inserted at path ending pins.

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“…However, they are usually more prone to PVT variations because they operate at a low supply voltage, and they remain limited by the threshold voltage of transistor devices. To overcome these design limitations, several LDOs with a digital control loop have been published in recent years [16][17][18][19][20][21][22]. Hwang et al [16] reported a digital error amplifier composed of a V-I conversion stage and an inverter-based latch to replace the conventional error amplifier.…”

Section: Introductionmentioning

confidence: 99%

“…However, using the shift register requires considerably more bit numbers if more loading current is desired, thereby consuming additional chip area. Based on the digital LDO proposed in [19], Hirairi et al [20] reported an adaptive power supply voltage control system for timing-critical ultralow voltage applications to cope with PVT variations. Hsieh and Hwang [21] reported a digitally controlled LDO using a phase comparison technique and multiple push-pull output stages.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology

Chen

2012

Microelectronics Journal

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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

Cited by 30 publications

References 3 publications

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology

SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology

A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology

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