14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

Sub-sampling PLL techniques

“…If the  pul sampling point is at the peak of a sine-wave, the gain would even be zero. One way to handle this issue as shown in [16] is to first convert the sine-wave into a more linear waveform like a sawtooth and then use an SSTDC to digitize the entire waveform. Digital background calibration can then be applied to linearize it.…”

“…The PD and CP noise is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the sub-sampling PLL techniques and their applications in recent PLL architectures [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Section II discusses the classical charge pump PLL.…”

In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies

“…During a fractional-N mode operation, the phase error between reference and oscillator will increase with time and thus the PLL fails to lock, as shown in Figure 3 In recent years, two approaches have been reported to achieve fractional-N operation SSPLL [54]- [58]. In this thesis, we name these two methods as reference-shifting subsampling (RS-SS) and alias-cancelling subsampling (AC-SS).…”

“…Another approach to fractional-N SSPLL is shown in Figure 3-10 [58]. which is generated in a fractional-N subsampling.…”

“…5 compares this work with other state-of-the-art multi-GHz fractional-N SSPLLs. Note that[54],[57], and[58] do achieve better jitter performance and lower in-band phase noise after the time-consuming calibrations. For a fair comparison, noise performance with and without calibration is also listed.…”