Sub-sampling PLL techniques

Abstract

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N 2 , when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter•power Figure-Of-Merit (FOM). A subsampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures.

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

“…is -124dBc/Hz at a 2.2GHz carrier with less than ±1dB variation for all digital codes, while the PLL alone without DTC showed -125dBc/Hz [29]. This shows the DTC is suitable for low-phase-noise applications.…”

“…In an attempt to still quantify the phase noise, we used a previously published low-jitter PLL [29] as a frequency multiplier with the setup in Fig. 21 (a).…”

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

“…analog-to-digital converters, optical data communication and RF front-ends. Sub-sampling phase-locked loops (SSPLLs) [1][2][3][4] have superior phase noise (PN) performance compared to conventional phase-frequency detector (PFD) PLLs. However, SSPLLs only reduce the closein PN.…”

Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking

“…Recently, subsampling technique has been proposed as an alternative approach to the conventional tri-state phase-frequency detector (PFD) to achieve greatly improved in-band phase noise [1]. The SSPLL in [2] uses a tri-state PFD with large dead-zone to switch between the regular frequency/phase loop (FPL) and the subsampling loop (SSL).…”

“…Furthermore, to achieve fractional frequency synthesis in subsampling mode, conventional methods involving toggling of frequency dividers and its associated sigma-delta noise shaping cannot be used directly, as VCO zero-crossing sampling by the SSL is wanted [1]. To resolve this problem, prior art has proposed to use digital-to-time converter (DTC) on the reference clock to offset this mismatch such that the reference edge remains aligned with the VCO zero-crossing even in fractional-N mode [4].…”