14-T hybrid full adder design and its implementation for high-performance arithmetic applications

Abdul, Azeem Mohammed; Prasanna, N.V.S.S.; Kumar, K.V. Harish; Teja, K. Banu

doi:10.1016/j.matpr.2022.09.137

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…Figure 11 and Figure 12 show the layouts obtained through Cadence Layout XL tool for the proposed Full Adder Cells. Table 2 illustrates the comparison results of Min and Max delay, Average delay, Power, PDP, transistor count and area requirement for each FA cell using several conventional and novel full adder styles discussed in our literature namelyC-CMOS [8], CMOS TG [9], Pseudo nMOS [10], PTL [11], , CVSL [12], CPL [13], DCVL [14], DCVSPG [13], , DPL [15], SRPL [16], SR-CPL [17], EEPL [18], Naseri (HFA-22T ) [21], Mehedi [22], Jyoti [23], Sharmila [24], Azeem [25], Rahimi [26], Proposed Logic 1 and Proposed Logic 2. Since proposed full adders are designed using DPL and they ensure the full voltage swing output in all the conditions.…”

Section: Simulation Environment Resultsmentioning

confidence: 99%

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Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

2024

Informacije MIDEM

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As the demand for computational capabilities continues to grow, the design and optimization of arithmetic circuits have more crucial in modern digital systems. The efficient operations of these arithmetic circuits heavily depend on the performance of fundamental modules such as Full Adders (FA). In addition to addressing typical challenges, designing full adder circuits using alternative logic offers unique advantages that are vital for the developing landscape of digital system. This paper presents two FAs based an alternative structures using modified Double Pass-Transistor Logic (DPL) for fast computing. The proposed Multiplexer based alternative structure differs from other conventional structures by concurrently generating both the carry signal and the sum signal, significantly reducing the overall propagation time. In addition to that multiplexers are controlled by external signals, the proposed structures provide full swing outputs. Also the modified DPL improves the signal integrity and noise immunity. The proposed circuits' performances were compared with other conventional logic and few hybrid adders. In comparison with other logics, various type of simulation results indicate that the proposed FA-2 exhibits improved performance in terms of average power, average delay, and average power-delay product (PDP). Our proposed FA-2 shows performance improvement over conventional CMOS for Power, Delay, and PDP, with values of 3.304%, 69.017%, and 74.602%, respectively. Full adders were simulated under different supply voltages and process corners to measure the reliability and robustness. Noise tolerances of full adder circuits were calculated using Average Noise Threshold Energy (ANTE) methodology.

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Section: Simulation Environment Resultsmentioning

confidence: 99%

“…Azeem et. al [25] introduced a high performance 14-T HFA using PTL and GDI logic for arithmetic applications. They pointed out that hybrid styles are most preferable for implementing FA cell in recent years.…”

Section: Introductionmentioning

confidence: 99%

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

2024

Informacije MIDEM

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A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder

Sharma,

Jhamb

2024

Circuits Syst Signal Process

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Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

Basha,

Gundala,

Madhurima

et al. 2024

Eng. Res. Express

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Energy Efficiency is of critical significance when designing integrated circuits. In the world of advanced integrated circuits (ICs) that operate in near-threshold voltage (NTV) is gaining much awareness because of its potential for high-performance and energy-efficient designs. But, the unique problems presented by near-threshold voltage process require meticulous analysis and development of basic arithmetic circuits that minimize the impact of the process's variations as well as fluctuations in supply voltage and additional performance limitations. In this brief, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for near threshold computing (NTC) application to conquer a unique module for achieving full swing borrow output. The proposed cell offers advantages by providing high-driving capacity for both difference and borrows outputs when integrated in multistage structures such as dividers, multipliers and compressors. Power, Delay, Energy and the product of Energy with Delay (EDP) metrics were evaluated, with comparison to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a entire die area of 60.02 μm2, while the power (average), delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. GLBB circuits achieve performance levels that are not affordable in conventional CMOS as well as DTMOS configurations. The outcomes demonstrate how efficient the FS cell can serve as an arithmetic circuit for unconventional signal processing computing applications in integrated circuits (ICs).

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14-T hybrid full adder design and its implementation for high-performance arithmetic applications

Cited by 4 publications

References 13 publications

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder

Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

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