16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor

Yemiscioglu, Gurtac; Lee, Peter

doi:10.1109/mwscas.2012.6291970

Cited by 9 publications

(6 citation statements)

References 11 publications

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“…This simple method has subsequently been developed and improved by many researchers since [22][23][24][25][26] and is the easiest to implement. Mitchell's algorithm finds the binary logarithm from a binary number by using a simple shifting and counting method.…”

Section: Mitchell's Linear Interpolation Methodsmentioning

confidence: 99%

“…There has been much research into logarithmic conversion [22][23][24][25][26] and, for simplicity the algorithms chosen here is based on the original work by Mitchell.…”

Section: Logarithmic Arithmetic and Conversion Algorithmsmentioning

confidence: 99%

“…For this architecture to be effective, efficient algorithms for converting to and from the logarithmic domain are required. The logarithm base‐2 (log 2 ( x )) of a number x is usually defined using a 4‐tuple 〈 Z , S , I , F 〉, where Z represents the zero bit, S is a sign bit, I is the integer part (characteristic) and F is the fractional part (mantissa) of a logarithm base‐2 respectively as shown in the following equation

x = 2^{false(\log_{2} false(x false) false)} = false(1 - Z false) false(- 1 {false)}^{S} 2^{I} 2^{0. F}

There has been much research into logarithmic conversion [22–26] and, for simplicity the algorithms chosen here is based on the original work by Mitchell.…”

Section: Logarithmic Arithmetic and Conversion Algorithmsmentioning

confidence: 99%

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Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor

Yemiscioglu

Lee

2015

IET Computers & Digital Techniques

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This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal-oxidesemiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm 2 . Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.

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Section: Mitchell's Linear Interpolation Methodsmentioning

confidence: 99%

“…There has been much research into logarithmic conversion [22][23][24][25][26] and, for simplicity the algorithms chosen here is based on the original work by Mitchell.…”

Section: Logarithmic Arithmetic and Conversion Algorithmsmentioning

confidence: 99%

x = 2^{false(\log_{2} false(x false) false)} = false(1 - Z false) false(- 1 {false)}^{S} 2^{I} 2^{0. F}

There has been much research into logarithmic conversion [22–26] and, for simplicity the algorithms chosen here is based on the original work by Mitchell.…”

Section: Logarithmic Arithmetic and Conversion Algorithmsmentioning

confidence: 99%

See 1 more Smart Citation

Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor

Yemiscioglu

Lee

2015

IET Computers & Digital Techniques

Self Cite

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“…Adiabatic logic [9][10][11][12][13][14][15][16] circuits are well known to achieve ultralow power by restricting the current flow across the device and recycling the energy of output node capacitances to the ac power supply. A plethora of adiabatic logic has been reported in the literature in the super-threshold regime [9][10][11][12][13][14] whereas very few have been detailed for the sub-threshold regime [15,16]. However, in depth analytical modelling of adiabatic logics for NTC has not been reported yet.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing

Chanda¹,

Mal²,

Mondal³

et al. 2018

IET Circuits, Devices & Systems

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The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator.

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“…The size of the battery increases with the increasing the demand of portable devices. Nowadays, various techniques have been developed and adiabatic technique is one of them which are also called reversible logic technique [1]. In conventional CMOS circuits, with the help of reducing supply voltage, node capacitance and switching frequency, power consumption can be minimized but recently adiabatic technique has been implemented very successfully in low power systems [2].…”

Section: Introductionmentioning

confidence: 99%