Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor

Yemiscioglu, Gurtac; Lee, Peter

doi:10.1049/iet-cdt.2014.0102

Cited by 9 publications

(5 citation statements)

References 30 publications

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“…Reducing the gate size reduces its capacitance May introduce delay Adiabatic switching [23,24] Recovers clocking energy Uses significantly less power than a conventional CMOS circuit [24]; relies on slow transition times…”

Section: Gate Sizingmentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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The projected rise in wireless communication traffic has necessitated the advancement of energy-efficient (EE) techniques for the design of wireless communication systems, given the high operating costs of conventional wireless cellular networks, and the scarcity of energy resources in low-power applications. The objective of this paper is to examine the paradigm shifts in EE approaches in recent times by reviewing traditional approaches to EE, analyzing recent trends, and identifying future challenges and opportunities. Considering the current energy concerns, nodes in emerging wireless networks range from limited-energy nodes (LENs) to high-energy nodes (HENs) with entirely different constraints in either case. In view of these extremes, this paper examines the principles behind energy-efficient wireless communication network design. We then present a broad taxonomy that tracks the areas of impact of these techniques in the network. We specifically discuss the preponderance of prediction-based energy-efficient techniques and their limits, and then discuss the trends in renewable energy supply systems for future networks. Finally, we recommend more context-specific energy-efficient research efforts and cross-vendor collaborations to push the frontiers of energy efficiency in the design of wireless communication networks.

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Section: Gate Sizingmentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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“…A 8*8 tree multiplier has been implemented using ECRL (Efficient Charge Recovery Logic) adiabatic design in 22nm CADENCE tool and 61.5% less power consumption was observed compared to conventional CMOS [4] . A 16 bit logarithmic signal processor has been implemented using clocked adiabatic logic in 0.35μm and 10 times less power consumption than conventional CMOS was achieved [5] . 2*2, 4*4 and 8*8 vedic multipliers have been implemented using EEAL(Energy Efficient Adiabatic Logic) and the researchers achieved power saving of 64.3%, 56% and 41% respectively in 0.18μm CADENCE [6] .…”

Section: State Of the Artmentioning

confidence: 99%

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Babu¹,

Sivakumar²

2018

J. Phys.: Conf. Ser.

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Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic.

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“…The use of adiabatic logic technique instead of the nonadiabatic logic design can considerably decrease the energy consumption in a large system [1]- [4], [8]- [11], [15]- [22]. Though it is in existence for more than two decades, still, its full potential has not been explored.…”

Section: Introductionmentioning

confidence: 99%

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

Maheshwari

Bartlett

Kale

2018

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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In comparison to conventional CMOS (nonadiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit updown counter, as a design example that demonstrates the practicality of the proposed approach.

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Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor

Cited by 9 publications

References 30 publications

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

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