Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing

Chanda, Manash; Mal, Sandipta; Mondal, Akash; Sarkar, Chandan Kumar

doi:10.1049/iet-cds.2017.0386

Cited by 14 publications

(3 citation statements)

References 22 publications

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“…Finally, our proposed work is compared with some state-of-the-art technologies (Chanda et al , 2018; Chanda et al , 2015). The power dissipation of a single stage adiabatic inverter is computed and compared with conventional CMOS inverter (Chanda et al , 2018), for which a performance matrix, called “energy gain” is defined. The energy gain is defined as the percentage of the ratio of dissipated power of an adiabatic inverter with COMS inverter.…”

Section: Circuit Implementation and Resultsmentioning

confidence: 99%

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Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Ghosh

Venkateswaran

Sarkar

2021

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Purpose High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit. Design/methodology/approach Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances. Findings The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter. Originality/value Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

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Section: Circuit Implementation and Resultsmentioning

confidence: 99%

“…Energy gain for adiabatic inverter (%)(Chanda et al, 2018) Energy gain for HTFET-based inverter (%) (proposed work)…”

mentioning

confidence: 99%

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Ghosh

Venkateswaran

Sarkar

2021

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“…In many research works, different types of adiabatic logic have been reported for low energy consumption, such as positive feedback adiabatic logic (PFAL) [1], modified positive feedback adiabatic logic (MPFAL) [2], efficient charge recovery logic (ECRL) [3], and energy-efficient adiabatic logic (EEAL) [3]. Subthreshold adiabatic logic (SAL) [4,5] utilizes the advantage of both the adiabatic logic [6,7] and subthreshold region of operation of CMOS logic. In adiabatic logic circuits, energy is recycled back to the source, so that to reduce total energy drawn from power source.…”

Section: Introductionmentioning

confidence: 99%

Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply

Prajapati

Shukla

Gupta

2020

Lecture Notes in Electrical Engineering

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Adiabatic logic has been found to be effective in achieving low power in VLSI circuits. In subthreshold region, the circuit conducts a small current and consumes lesser power. In this paper, the dual rail power supply with 0 and 180°phase difference has been used for subthreshold adiabatic logic (SAL). A priority encoder is designed using SAL with dual rail power supply. All the circuit simulations are done using HSPICE simulator at 22 nm PTM technology. In-phase dual supply offers low power consumption, whereas out-phase dual power supply offers an improved noise margin.

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Power-Efficient Code Converters Using Sub-Threshold Adiabatic Logic Ultra-Low-Power Applications

Gaurav

Prashant

Singh

2021

Proceedings of International Conference on Communication and Artificial Intelligence

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Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing

Cited by 14 publications

References 22 publications

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply

Power-Efficient Code Converters Using Sub-Threshold Adiabatic Logic Ultra-Low-Power Applications

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