19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS

Rahman, Fahim; Pamula, Rajesh; Boora, Akshat; Sun, Xun; Sathe, Visvesh

doi:10.1109/isscc.2019.8662486

Cited by 6 publications

(3 citation statements)

References 3 publications

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“…The MEP technique can accurately manage energy consumption to extend the life of Internet of Everything (IoE) devices. However, if the processor requires higher performance and the MEP technique violates the timing constraints, the Cortex-M0 is switched to the performancelock mode at an operational voltage VOUT equal to the target voltage Vtarg, which is a sufficiently high voltage [2], to guarantee sufficient supply voltage. Although a cascaded switched-capacitor regulator can be used to supply the target voltage Vtarg, the efficiency is degraded because the supplying voltage is fixed in [2]- [3].…”

Section: Proposed Medp Modementioning

confidence: 99%

“…However, if the processor requires higher performance and the MEP technique violates the timing constraints, the Cortex-M0 is switched to the performancelock mode at an operational voltage VOUT equal to the target voltage Vtarg, which is a sufficiently high voltage [2], to guarantee sufficient supply voltage. Although a cascaded switched-capacitor regulator can be used to supply the target voltage Vtarg, the efficiency is degraded because the supplying voltage is fixed in [2]- [3]. Therefore, to meet the operational performance at the lowest energy, the switchable control between MEP and MEDP modes in Fig.…”

Section: Proposed Medp Modementioning

confidence: 99%

“…3(b), the accuracy of Minimum Energy Point (MEP) in Fig. 4(a) can be improved compared with [2] and [3]. Moreover, adding the delay information to generate an alternative minimum energy delay point (MEDP) mode in Fig.…”

Section: Introductionmentioning

confidence: 99%

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A Series Stacked FinFET Structure for Digital Low Dropout Regulators with Minimum Energy Point Technique for 37.5% Energy Reduction in Cortex M0 Processor

Tseng

Huang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively. Keywords-series stacked (SS) FinFET, dynamic voltage scaling (DVS) technique, minimum energy point (MEP) technique.

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Section: Proposed Medp Modementioning

confidence: 99%