19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS

Shen, Kun-Yi; Farooq, Syed Feruz Syed; Fan, Y.; Nguyen, Kimchau N.; Wang, Qi; Elshazly, Amr; Kurd, Nasser

doi:10.1109/isscc.2016.7418041

Cited by 24 publications

(12 citation statements)

References 3 publications

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“…The 33X better energy-efficiency warrants for a practical implementation which would be a future extension of this work. Our work achieves a better pJ/cycle number because of (1) no additional spur-cancelation circuit (for narrowband applications such as [22]) is required because the PLL output for a BB-BAN will not be subjected to mixing and its nonidealities, (2) no active circuit for adaptive BW control (as no real-time self-adjustment is needed for BB-BAN) and no integral/proportional charge pump as in [10], [20] and [21] is employed, (3) VCO and LDO, which are two of the most power-intensive components in a PLL, are optimized for a low (f/fT) application, (4) no replica-feedback (as in [9]) and no additional noise cancellation circuit (as in [19]) is needed as LDO provides -50dB PSNR for the frequency of operation. The wide tuning range is achieved because of the scalable VCO and adjustable loop BW.…”

Section: Resultsmentioning

confidence: 99%

Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range

Mehrotra

Chatterjee

Maity

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, we present the design considerations for a sub-25μW phase-locked loop (PLL) with a wide tuning range and multi-phase outputs, which makes it suitable for applications that involve clock-and-data-recovery with variable data rates, such as broadband body-area-networks. Several architectures for the voltagecontrolled-oscillator (VCO) are analyzed for power and performance, and the considerations for keeping the VCO's low-dropout-regulator (LDO) within the loop and outside the loop are discussed. Power consumption is minimized by keeping the LDO outside the loop, which exempts the error-amplifier (EA) from the bandwidth constraints posed by the PLL. Conforming to the analysis, the PLL is designed and simulated in a standard 65nm CMOS process, and the results show that energy-efficiencies as low as 70fJ/cycle can be achieved with a tuning range of 1-450MHz along with multi-phase outputs with RMS timing jitter of 11.4ps (frequency offset < 100ppm) from a 31-stage split-tuned ring oscillator VCO.

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Section: Resultsmentioning

confidence: 99%

Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range

Mehrotra

Chatterjee

Maity

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Therefore, passive filters are inserted between the current copy transistors, so the thermal and flicker noise from the bias generating transistors can be suppressed. In addition, C LF helps improve power supply rejection ratio (PSRR) [19].…”

Section: Digitally Controlled Oscillatormentioning

confidence: 99%

A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

Kim

Jin

et al. 2022

Electronics

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A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.

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“…The PLL based on self-biased techniques is attractive for solving these problems [11][12][13][14][15]. The self-biased PLL has the following advantages:…”

Section: Of 15mentioning

confidence: 99%

“…However, many self-biased PLLs [11][12][13] whose loop bandwidth cannot track the division ratio have removed the division ratio effect, and the bandwidth is unchanged when the reference clock is stable. The low-pass filter (LPF) is a key module in PLL.…”

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confidence: 99%

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A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Tian

et al. 2021

Electronics

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This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

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19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS

Cited by 24 publications

References 3 publications

Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range

Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range

A Referenceless Digital CDR with a Half-Rate Jitter-Tolerant FD and a Multi-Bit Decimator

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

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