1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS

Okamoto, Yuki; Komura, Yoshiaki; Mizuguchi, T.; Saito, Toshihiko; Ito, Masaya; Kimura, Kiyoshi; Onuki, Tatsuya; Ando, Yasuhisa; Sawai, Hiromi; Murakawa, Tsutomu; Kunitake, Hitoshi; Matsuzaki, Takashi; Kimura, Hajime; Fujita, Masahiro; Ikeda, Makoto; Yamazaki, Shunpei

doi:10.23919/vlsitechnologyandcir57934.2023.10185263

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2024

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Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM

Inoue,

Hirose,

Mizuguchi

et al. 2024

2024 IEEE International Memory Workshop (IMW)

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Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM

Inoue,

Hirose,

Mizuguchi

et al. 2024

2024 IEEE International Memory Workshop (IMW)

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1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

Hirose,

Okamoto,

Komura

et al. 2024

IEEE J. Electron Devices Soc.

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We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an 2.2  10 -19 A/cell at 85C), indicating that over 99 of the data are retained in the memory array after one hour at 85C without refresh.

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CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Wang,

Zheng,

Lin

et al. 2024

IEEE Trans. Electron Devices

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1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS

Cited by 3 publications

References 0 publications

Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM

Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM

1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs

CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

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