2:1 Multiplexer based design for ternary logic circuits

Vudadha, Chetan; Katragadda, Sowmya; Phaneendra, P. Sai

doi:10.1109/primeasia.2013.6731176

Cited by 15 publications

(13 citation statements)

References 11 publications

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“…Ternary logic has three logic values (logic 0, logic 1 and logic 2) while Quaternary logic has four logic values. Major problems with usage of two level logic are interconnection problem that arises inside the chip and also among the chips (Vudadha et al, 2013). As number of logic elements in the chip are increasing every year, positioning and interconnection of those logic elements are creating problems for the designers; chip area required for interconnecting logic elements are more than the area required for placing of all the logic elements (Hurst et al, 1984).…”

Section: Introductionmentioning

confidence: 99%

“…In this circuit design four ternary multiplexers are used due to which large number of transistors are required which significantlt increases increases the dealy and power consumption. In(Vudadha et al, 2013) in this proposed design 2x1 mux with some additional circuitry ared used to remove some of the 3x1 mux from the design proposed in(Vudadha et al, 2012), due to this number of transistors can be reduced. In(Vudadha et al, 2013) instead of four 3x1 mux, two 3x1 mux and two 2x1 mux with some additional circuitry are used to built ternary half adder circuit.…”

mentioning

confidence: 99%

“…In(Vudadha et al, 2013) in this proposed design 2x1 mux with some additional circuitry ared used to remove some of the 3x1 mux from the design proposed in(Vudadha et al, 2012), due to this number of transistors can be reduced. In(Vudadha et al, 2013) instead of four 3x1 mux, two 3x1 mux and two 2x1 mux with some additional circuitry are used to built ternary half adder circuit. This design consumes less power and delay is also reduced than design proposed in(Lin et al, 2011)(Vudadha et al, 2012).…”

mentioning

confidence: 99%

See 2 more Smart Citations

Ternary Logic Circuits Using Cntfet: A Brief Review

Yadav¹,

Nair²

2020

IJEAST

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A brief review about carbon nanotube is presented at first, followed by nnnnnna brief review of ternary logic and then finally some of the ternary logic circuit built with carbon nanotube field effect transistor (CNTFET) are discussed. Recent progress in ternary logic circuit proposed by using CNTFET as basic building block is discussed in this paper. Complementary CNTFET designs are used to build ternary logic circuits just like Complementary CMOS designs. MVL has gained its popularity as binary logic circuits are reaching its limitations. Different CNTFET Ternary logic circuits like half adder (HA), full adder (FA) and multiplier circuits are studied and a brief review is presented in this paper about how different designs and different methodologies are proposed to achieve high performance, low power consuming and also with less delay.

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Ternary Logic Circuits Using Cntfet: A Brief Review

Yadav¹,

Nair²

2020

IJEAST

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“…Except few current mode circuits, such as the MVL states were defined in terms of an integral multiple of reference current [4], most MVLs are realised on the voltage mode. In this mode, multi‐threshold COMS logic [5] and negative differential resistance (NDR) logic are the common ones.…”

Section: Introductionmentioning

confidence: 99%

Multi‐valued logic design methodology with double negative differential resistance transistors

Chang

Wang

et al. 2017

Micro & Nano Letters

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Multi-valued logic (MVL) is one of the promising alternatives of binary logic since it has a high-logic density, which brings a vision of simpler circuit structure. Based on a novel concept as double negative differential resistance field effect transistor and its analytic description, a design methodology utilising the mechanism of monostable-to-multistable transition logic element (MMLE) for MVL is proposed in this study. The basic ternary logic gates are designed as a complete logic set, and a compact ternary four-input full adder is constructed as an example of function circuits. Comparing with binary circuit and ternary circuit based on conventional design, the circuit shows advantage in device cost and other properties. The results verify that this MMLE design methodology has a good information load ability, which will have a brilliant prospect in MVL circuits.

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“…For instance, more data can be transmitted over an arrangement of lines in a given length, diminishing in the complexity of interconnections is observed, decrease in chip area can be accomplished, and more significantly the error detection and error correction of codes can be accomplished. The ternary logic system has some significant merits over the binary logic system [2,3]. To implement the different logic functions, the decrease in the number of interconnections in a circuit is observed, in this way, the chip area has been reduced, and importantly more data can be transmitted and lesser memory is required.…”

mentioning

confidence: 99%

Design and Implementation of Ternary Logic Circuits for VLSI Applications

Thrishala*¹,

Ragini²

2020

IJITEE

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This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count.

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2:1 Multiplexer based design for ternary logic circuits

Cited by 15 publications

References 11 publications

Ternary Logic Circuits Using Cntfet: A Brief Review

Ternary Logic Circuits Using Cntfet: A Brief Review

Multi‐valued logic design methodology with double negative differential resistance transistors

Design and Implementation of Ternary Logic Circuits for VLSI Applications

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